Issues and optimization of millisecond anneal process for 45 nm node and beyond

We have investigated millisecond anneal, such as laser spike annealing (LSA) and flash lamp annealing (FLA), which substitute for spike RTA as a dopant activation technology of source/drain extension for 45 nm node. Three key issues of gate leakage current, junction leakage current and pattern dependence were discussed from the integration and CMOSFETs performance viewpoint. We reported that LSA is the leading candidate for 45 nm node and beyond.

[1]  C.C. Chen,et al.  65nm CMOS high speed, general purpose and low power transistor technology for high volume foundry application , 2004, Digest of Technical Papers. 2004 Symposium on VLSI Technology, 2004..

[2]  A. Hiraiwa,et al.  Ultra-shallow junction formation by non-melt laser spike annealing for 50-nm gate CMOS , 2004, Digest of Technical Papers. 2004 Symposium on VLSI Technology, 2004..

[3]  K. Suguro,et al.  10–15 nm Ultrashallow Junction Formation by Flash-Lamp Annealing , 2002 .