Ultrahigh Density VLSI Inner Product Computations

This paper discusses some of the limitations to matrix computations performed by special-purpose VLSI systems on a chip as the minimum feature size of CMOS technology is reduced to below 1.0 µm. Limits to computation rates are imposed by power dissipation and by having a maximum number of pins or input/output ports on the package. The analysis applies to regular networks of array multipliers performing binary integer arithmetic at various bit precisions.