RRANN: the run-time reconfiguration artificial neural network

Run-time reconfiguration is a way of more fully exploiting the flexibility of reconfigurable field programmable gate arrays (FPGAs). The run-time reconfiguration artificial neural network (RRANN) uses runtime reconfiguration to increase the hardware density of FPGAs. This is done by dividing the backpropagation algorithm into three sequentially executed stages and configuring the FPGAs to execute only one stage at a time. The FPGAs are reconfigured as part of normal execution in order to change stages. Using reconfigurability in this way increases the number of hardware neurons a single FPGA can implement by 500%. The RRANN architecture has been designed and built using commercially available hardware, and its performance has been measured.<<ETX>>

[1]  D. Hammerstrom,et al.  A VLSI architecture for high-performance, low-cost, on-chip learning , 1990, 1990 IJCNN International Joint Conference on Neural Networks.

[2]  Geoffrey E. Hinton,et al.  Learning internal representations by error propagation , 1986 .

[3]  Neil Weste,et al.  Principles of CMOS VLSI Design , 1985 .

[4]  Kamran Eshraghian,et al.  Principles of CMOS VLSI Design: A Systems Perspective , 1985 .

[5]  T. Watanabe,et al.  Neural network simulation on a massively parallel cellular array processor: AAP-2 , 1989, International 1989 Joint Conference on Neural Networks.

[6]  Brad Hutchings,et al.  Density enhancement of a neural network using FPGAs and run-time reconfiguration , 1994, Proceedings of IEEE Workshop on FPGA's for Custom Computing Machines.