On-chip sampling sensors for high frequency signals measurement: evolution and improvements

Due to increasing speed and complexity, integrated circuits (ICs) are faced with severe parasitic problems: signal glitch, supply, crosstalk induced delay, substrate coupling. Various measurement techniques have been developed in order to observe these effects. Off-chip methodologies such as E-beam sampling, direct probing or S-parameters, allow to probe some parasitic phenomena, but they have strong limitations in term of bandwidth, invasive probes, complex setup or cost. In this paper, an overview of different on-chip measurement systems is presented. An on-chip sampling technique is detailed and we describe the applications for which this sensor has succeeded to provide accurate measurements. Sensor performances are compared for four CMOS technologies (0.7/spl mu/m, 0.35/spl mu/m, 0.18/spl mu/m and 90nm). In the last part, we present an improved sensor which measures all parasitic phenomena in the full supply range.

[1]  Toshiro Tsukada,et al.  Voltage-comparator-based measurement of equivalently sampled substrate noise waveforms in mixed-signal integrated circuits , 1996 .

[2]  C. Svensson,et al.  Measuring high-bandwidth signals in CMOS circuits , 1993 .

[3]  Shoichi Masui,et al.  Experimental results and modeling techniques for substrate noise in mixed-signal integrated circuits , 1993 .

[4]  P. Wambacq,et al.  A design experiment for measurement of the spectral content of substrate noise in mixed-signal integrated circuits , 1999, 1999 Southwest Symposium on Mixed-Signal Design (Cat. No.99EX286).

[5]  Yu Zheng,et al.  On-chip oscilloscopes for noninvasive time-domain measurement of waveforms in digital integrated circuits , 2003, IEEE Trans. Very Large Scale Integr. Syst..

[6]  J. Cabestany,et al.  A test structure for E-beam testing , 1993, ICMTS 93 Proceedings of the 1993 International Conference on Microelectronic Test Structures.

[7]  Krishnamurthy Soumyanath,et al.  Accurate on-chip interconnect evaluation: a time-domain technique , 1999 .

[8]  J.C. Chen,et al.  An on-chip, interconnect capacitance characterization method with sub-femto-farad resolution , 1997, 1997 IEEE International Conference on Microelectronic Test Structures Proceedings.

[9]  Gordon W. Roberts,et al.  A high speed and area efficient on-chip analog waveform extractor , 1998, Proceedings International Test Conference 1998 (IEEE Cat. No.98CH36270).

[10]  Miquel Roca,et al.  Measurement of crosstalk-induced delay errors in integrated circuits , 1997 .

[11]  W. R. Eisenstadt,et al.  S-parameter-based IC interconnect transmission line characterization , 1992 .

[12]  Robert H. Dennard,et al.  Modeling and characterization of long on-chip interconnections for high-performance microprocessors , 1995, IBM Journal of Research and Development.