On Feasibility of FPGA Bitstream Compression During Placement and Routing
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[1] Guido Masera,et al. A new approach to compress the configuration information of programmable devices , 2006, Proceedings of the Design Automation & Test in Europe Conference.
[2] I. Xilinx. Virtex series configuration architecture user guide , 2000 .
[3] Vaughn Betz,et al. Architecture and CAD for Deep-Submicron FPGAS , 1999, The Springer International Series in Engineering and Computer Science.
[4] I. Xilinx,et al. Virtex? 2. 5v field programmable gate arrays , 2000 .
[5] Carl Carmichael. Virtex FPGA series configuration and readback , 1999 .
[6] Zhiyuan Li,et al. Configuration Compression for Virtex FPGAs , 2001, The 9th Annual IEEE Symposium on Field-Programmable Custom Computing Machines (FCCM'01).
[7] Giovanni Squillero,et al. RT-Level ITC'99 Benchmarks and First ATPG Results , 2000, IEEE Des. Test Comput..
[8] Naveed A. Sherwani,et al. Algorithms for VLSI Physical Design Automation , 1999, Springer US.