Buried interfacial gate oxide for tri-gate negative-capacitance fin field-effect transistors: approach and investigation

Negative-capacitance fin field-effect transistors (NC-FinFETs), due to their superior gate electrostatics and dominance over short channel effects (SCEs), have been a key technology among conventional devices. The improved device performance in terms of the various engineering practices has paved the way for the advancement of NC-FinFETs. In the following work, we have proposed a novel buried oxide strategy for the NC-FinFET architecture, in which we have altered the depth of the interfacial gate oxide (IGO) layer inside the channel and analyzed the performance characteristics using TCAD Sentaurus. First, we varied the IGO thickness that was buried inside the channel and performed a comparative analysis between the DC, mixed-mode, and SCE parameters for the various buried configurations of the proposed NC-FinFET in order to realize the optimized depth. We also present the tolerable degradation in the circuit characteristics that occurs with the varying buried IGO (BIGO) depth. It can be inferred from the presented interface trap discussion that the idea of BIGO thickness holds well for low-power electronics.