A New Transistor-Level Circuit for Modified Booth's Encoder

Design of a new high speed, low power and area efficient circuit for Modified Booth's Encoder is presented in the paper This circuit combines the CMOS logic circuits and pass transistor (PT) logic circuits By utilizing the new high speed low power XOR and XNOR circuits, only 30 transistors are used to implement the Modified Booth's Algorithm Experimental results showed that the worst case delay of the new circuit, which is based on a 0 35μm CMOS process, is 0 34 ns at a supply voltage of 3 3 V, and the average power dissipation is 0 13 mW at 100 MHz