Multiple-input, multiple-output pass transistor logic

Techniques are presented for the design of multiple-input, multiple-output pass transistor circuits. By using shared functions as map-entered variables, dramatic reductions in transistor count can be achieved. Applied to a Viterbi decoder design for NASA, the transistor count of a CMOS integrated circuit was reduced by nearly 100 000 transistors over the best previously known techniques. A proof is presented which lowers the known theoretical upper bound on transistor count for circuits with six or more input variables. The implementation of practical single-output functions of less than six input variables is also shown to benefit from these techniques.