A 110-K transistor 25-MPixels/s configurable image transform processor unit

A configurable architecture for performing image transform algorithms is presented that provides a better tradeoff between low complexity and algorithm flexibility than either software-programmable processors or dedicated ASIC's. The configurable processor unit requires only 110 K transistors and can execute several image transform algorithms. By emulating the signal flow of the algorithms in hardware, rather than software, complexity is reduced by an order of magnitude compared with current software programmable video signal processors, while providing more flexibility than single function ASIC's. The processor has been fabricated in 1.2-/spl mu/m CMOS and has been successfully used to execute the discrete cosine transform/inverse discrete cosine transform (DCT/IDCT), subband coding, vector quantization, and two-dimensional filtering algorithms at pixel rates up to 25 MPixels/s.

[1]  P. A. Ruetz,et al.  The architectures and design of a 20-MHz real-time DSP chip set , 1989 .

[2]  Cliff Reader.  MPEG4: coding for content, interactivity, and universal accessibility , 1996 .

[3]  Hironori Yamauchi,et al.  Architecture and implementation of a highly parallel single-chip video DSP , 1992, IEEE Trans. Circuits Syst. Video Technol..

[4]  Peter A. Ruetz,et al.  A high-performance full-motion video compression chip set , 1992, IEEE Trans. Circuits Syst. Video Technol..

[5]  Hamid Gharavi,et al.  Subband coding algorithms for video applications: videophone to HDTV-conferencing , 1991, IEEE Trans. Circuits Syst. Video Technol..

[6]  R. Dianysian,et al.  Systolic Tree-Searched Vector Quantizer for Real-Time Image Compression , .

[7]  S. Purcell,et al.  A single chip multistandard video codec , 1993, Proceedings of IEEE Custom Integrated Circuits Conference - CICC '93.

[8]  Sehat Sutardja,et al.  A 50 MHz vision processor , 1991, Proceedings of the IEEE 1991 Custom Integrated Circuits Conference.

[9]  Jan M. Rabaey,et al.  A reconfigurable multiprocessor IC for prototyping of real-time data paths , 1992, 1992 IEEE International Solid-State Circuits Conference Digest of Technical Papers.

[10]  H. Yamada,et al.  A 250MHz 16b 1-million Transistor BICMOS Super-high-speed Video Signal Processor , 1991, 1991 IEEE International Solid-State Circuits Conference. Digest of Technical Papers.

[11]  G.A. Uvieghara,et al.  A real time P*64/MPEG video encoder chip , 1993, 1993 IEEE International Solid-State Circuits Conference Digest of Technical Papers.

[12]  D. M. Pfeiffer,et al.  A Parallel Image Processor Chip , 1988, 1988 IEEE International Solid-State Circuits Conference, 1988 ISSCC. Digest of Technical Papers.

[13]  Christopher J. Terman,et al.  A video decoder for H.261 video teleconferencing and MPEG stored interactive video applications , 1993, 1993 IEEE International Solid-State Circuits Conference Digest of Technical Papers.

[14]  R. Jain,et al.  An interleaved/retimed architecture for the lattice wave digital filter , 1991 .

[15]  T. Noguchi,et al.  A 15-ns 32*32-b CMOS multiplier with an improved parallel structure , 1990 .

[16]  R. Jain,et al.  An 80 k-transistor configurable 25 MPixels/s video compression processor unit , 1994, Proceedings of IEEE International Solid-State Circuits Conference - ISSCC '94.

[17]  S. Turner,et al.  A complete single-chip implementation of the JPEG image compression standard , 1991, Proceedings of the IEEE 1991 Custom Integrated Circuits Conference.

[18]  Rajeev Jain,et al.  An integrated circuit design for pruned tree-search vector quantization encoding with an off-chip controller , 1992, IEEE Trans. Circuits Syst. Video Technol..

[19]  Jan M. Rabaey,et al.  An integrated CAD system for algorithm-specific IC design , 1991, IEEE Trans. Comput. Aided Des. Integr. Circuits Syst..