Fault Tolerant ALU using Parity Preserving Reversible Logic Gates

Demand of reliable computing has been a major concern since the dawn of the electronic digital computer age. Reliable computing has various applications not only in the field of military, aerospace and communication but even contemporary commercial applications to fulfill today’s automated life style. The tremendous growth in fabrication from small scale integration (SSI) to giant scale integration (GSI) is facing power dissipation as one of the main barriers. To overcome this barrier, researchers need to enter into the reversible logic domain. Making a reversible circuit robust or fault tolerant is much more difficult than a conventional logic circuit. Fault tolerance can be achieved in a system by using parity bits. The main aim of this paper is to come up with a new fault tolerant ALU design based on parity preserving reversible logic gates with improved quantum cost and power overhead as compare to existing fault tolerance based ALU designs. The most stringent requirement for fault tolerant ALU is in real time control system where faulty computation jeopardizes human life or other catastrophic effects.Implentation of proposed design is done using Xilinx ISE design suit 14.2 tool and its performance over existing ALU designs is qualitatively analyzed.

[1]  Rakshith Saligram,et al.  Parity preserving logic based fault tolerant reversible ALU , 2013, 2013 IEEE CONFERENCE ON INFORMATION AND COMMUNICATION TECHNOLOGIES.

[2]  A. V. N. Tilak,et al.  Reversible Arithmetic Logic Unit , 2011, 2011 3rd International Conference on Electronics Computer Technology.

[3]  Mohammad Mortazavi,et al.  Analyzing Area Penalty of 32-Bit Fault Tolerant ALU Using BCH Code , 2011, 2011 14th Euromicro Conference on Digital System Design.

[4]  Zhijin Guan,et al.  An Arithmetic Logic Unit design based on reversible logic gates , 2011, Proceedings of 2011 IEEE Pacific Rim Conference on Communications, Computers and Signal Processing.

[5]  Varadan Savulimedu Veeravalli.  Fault tolerance for arithmetic and logic unit , 2009, IEEE Southeastcon 2009.

[6]  J. Senthil Kumar,et al.  Design and Implementation of a Reversible Logic Based 8-Bit Arithmetic and Logic Unit , 2014 .

[7]  Naman Sharma,et al.  Power Efficient Arithmetic Logic Unit Design using Reversible Logic , 2015 .

[8]  Matthew Morrison,et al.  Design of a novel reversible ALU using an enhanced carry look- ahead adder , 2011, 2011 11th IEEE International Conference on Nanotechnology.

[9]  A. Majumdar,et al.  Fault Tolerant ALU System , 2012, 2012 International Conference on Computing Sciences.

[10]  Bibhash Sen,et al.  Reversible Logic-Based Fault-Tolerant Nanocircuits in QCA , 2013 .

[11]  Charles H. Bennett,et al.  Logical reversibility of computation , 1973 .

[12]  Rakshith Saligram,et al.  Design of Parity Preserving Logic Based Fault Tolerant Reversible Arithmetic Logic Unit , 2013, VLSIC 2013.

[13]  Md. Saiful Islam,et al.  Reversible Logic Synthesis of Fault Tolerant Carry Skip BCD Adder , 2009, ArXiv.