23.3 A 4.8Gb/s/pin 2Gb LPDDR4 SDRAM with sub-100µA self-refresh current for IoT applications

The internet of things (IoT) requires that more data are collected and processed by devices with faster response, but lower power consumption. In order to achieve these unprecedented requirements, a high-speed DRAM with low-power dissipation at standby and during low-frequency operation in a small footprint is necessary. In addition, a higher degree of reliability is expected for some applications: such as transportation and healthcare. One promising solution, on-chip error correction coding (ECC), has gained traction among memory companies [1] and is now required by the LPDDR4 standard for the first time [2]. In this paper, a 2Gb LPDDR4 that dissipates 75% less refresh current than a conventional LPDDR4 is presented. The proposed LPDDR4 exploits ECC to reduce refresh current, periodically activated voltage regulators to reduce standby power, and dual CA buffers to save the buffer current during low frequency operation. In addition, circuit designs for cell screen of DRAM with on-chip ECC, and for high-speed wafer test for known good die (KGD) - essential for small form factor devices using system-in-package (SiP) - are presented.