Early Power Estimation for System-on-Chip Designs

Reduction of chip packaging and cooling costs for deep submicron System-On-Chip (SOC) designs is an emerging issue. We present a simulation-based methodology able to realistically model the complex environment in which a SOC design operates in order to provide early and accurate power consumption estimation. We show that a rich functional test bench provided by a designer with a deep knowledge of a complex system is very often not appropriate for power analysis and can lead to power estimation errors of some orders of magnitude. To address this issue, we propose an automatic input sequence generation approach based on a heuristic algorithm able to upgrade a set of test vectors provided by the designer. The obtained sequence closely reflects the worst-case power consumption for the chip and allows looking at how the chip is going to work over time.

[1]  Jörg Henkel,et al.  A framework for estimation and minimizing energy dissipation of embedded HW/SW systems , 1998, DAC.

[2]  Felice Balarin,et al.  Synchronous equivalence for embedded systems: a tool for design exploration , 1999, 1999 IEEE/ACM International Conference on Computer-Aided Design. Digest of Technical Papers (Cat. No.99CH37051).

[3]  Niraj K. Jha,et al.  COSYN: hardware-software co-synthesis of embedded systems , 1997, DAC.

[4]  Luciano Lavagno,et al.  Efficient power co-estimation techniques for system-on-chip design , 2000, DATE '00.

[5]  Srinivas Devadas,et al.  A computer-aided design methodology for low power sequential logic circuits , 1996 .

[6]  Massoud Pedram,et al.  High-level Power Modeling, Estimation, And Optimization , 1997, Proceedings of the 34th Design Automation Conference.

[7]  Srinivas Devadas,et al.  Computer-Aided Design Techniques for Low Power Sequential Logic Circuits , 1996 .

[8]  Miodrag Potkonjak,et al.  System-level synthesis of low-power hard real-time systems , 1997, DAC.

[9]  Massoud Pedram,et al.  Low power design methodologies , 1996 .

[10]  Luciano Lavagno,et al.  Hardware-software co-design of embedded systems: the POLIS approach , 1997 .

[11]  Anantha P. Chandrakasan,et al.  Low Power Digital CMOS Design , 1995 .

[12]  Luca Benini,et al.  Dynamic power management - design techniques and CAD tools , 1997 .

[13]  Luciano Lavagno,et al.  Hardware-Software Co-Design of Embedded Systems , 1997 .

[14]  Luca Benini,et al.  Dynamic Power Management , 1998 .

[15]  Jörg Henkel.  A low power hardware/software partitioning approach for core-based embedded systems , 1999, DAC '99.