A 4-GS/s 8-bit two-channel time-interleaved folding and interpolating ADC

Ultra high speed and moderate resolution ADCs with low latency are demanded in many applications. A 4-GS/s 8-bit ADC is implemented in the 0.35 μm SiGe BiCMOS technology. It is based on the two-channel time-interleaved architecture and each sub-ADC employs the two-stage cascaded folding and interpolating topology which guarantees the low-latency property. Calibration circuits are introduced to compensate for the mismatch between the two sub-ADCs. The whole chip area is about 4.0 × 4.0 (mm2). The ADC exhibits DNL of 0.26/−0.34 LSB and INL of 0.96/−0.92 LSB. The ENOB is 7.1 bits and the SFDR is about 56 dB at 10.1 MHz input. The SNDR is above 42 dB over the first and the second Nyquist zone. The SFDR is above 45 dB over the first Nyquist zone and the second Nyquist zone. The ERBW is about 1.4 GHz.

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