Impact of the on-chip and off-chip ESD protection network on transient-induced latch-up in CMOS IC

Measurements and mixed-mode simulations are used for the analysis of transient-induced latch-up (TLU) in CMOS IC. The transient interaction of the parasitic SCR with the surrounding off-chip and on-chip circuitry is investigated during positive and negative system-level ESD stress. It is shown, that sufficient on-chip decoupling and an active clamp can improve the TLU robustness of a circuit.

[1]  Harald Gossner,et al.  Study of system ESD codesign of a realistic mobile board , 2011, EOS/ESD Symposium Proceedings.

[2]  Ming-Dou Ker,et al.  Component-Level Measurement for Transient-Induced Latch-up in CMOS ICs Under System-Level ESD Considerations , 2006, IEEE Transactions on Device and Materials Reliability.

[3]  Yung C. Liang,et al.  Diode forward and reverse recovery model for power electronic SPICE simulations , 1990 .

[4]  K. Esmark,et al.  Triggering of Transient Latch-up by System-Level ESD , 2011, IEEE Transactions on Device and Materials Reliability.

[5]  Gerd Vandersteen,et al.  System-Level ESD Protection Design Using On-Wafer Characterization and Transient Simulations , 2014, IEEE Transactions on Device and Materials Reliability.

[6]  G. Groeseneken,et al.  Mixed-mode simulations for power-on ESD analysis , 2012, Electrical Overstress / Electrostatic Discharge Symposium Proceedings 2012.

[7]  Mirko Scholz,et al.  ESD On-Wafer Characterization: Is TLP Still the Right Measurement Tool? , 2009, IEEE Transactions on Instrumentation and Measurement.

[8]  T. Suzuki,et al.  A study of relation between a power supply ESD and parasitic capacitance , 2005, 2005 Electrical Overstress/Electrostatic Discharge Symposium.

[9]  G. Groeseneken,et al.  Characterization and modeling of transient device behavior under CDM ESD stress , 2004, 2003 Electrical Overstress/Electrostatic Discharge Symposium.