Experimental and theoretical analysis of factors causing asymmetrical temperature dependence of Vt in High-k Metal gate CMOS with capped High-k techniques

Temperature (T) dependence of threshold voltage (V<sub>t</sub>) for high-k metal gate stack (HK/MG) CMOS is investigated thoroughly. It is found, for the first time, that T dependence of V<sub>t</sub> (dV<sub>t</sub>/dT) for HK/MG CMOS shows asymmetrical behavior between N and PFETs unlike conventional Poly-Si/SiON CMOS. Moreover, this dV<sub>t</sub>/dT asymmetry is observed even if capping techniques for V<sub>t</sub> tuning are applied to high-k dielectrics. The position of effective Fermi level in HK/MG (E<sub>FM,eff</sub>) is determined quantitatively in a wide range of T by experimental and theoretical analysis for the first time, which reveals that the off-center arrangement of E<sub>FM,eff</sub> in Si band gap is the cause of dV<sub>t</sub>/dT asymmetry not only in the long channel region but also in the short channel region. In addition, based on these analyses, dV<sub>t</sub>/dT for aggressively thinned FinFETs with HK/MG is predicted.