A New Method for Layout-Dependent Parasitic Capacitance Analysis and Effective Mobility Extraction in Nanoscale Multifinger MOSFETs

The impact of layout-dependent parasitic capacitances on extraction of inversion carrier density <i>Q</i><sub>inv</sub> and effective mobility μ<sub>eff</sub> has been investigated on multifinger MOSFETs. An improved open deembedding method can eliminate the extrinsic parasitic capacitance, and 3-D interconnect simulation is necessary for extraction of intrinsic parasitic capacitances such as gate finger sidewall and finger-end fringing capacitances, i.e., <i>C</i><sub>of</sub> and <i>Cf</i>(poly-end), respectively. Both categories of parasitic capacitance lead to overestimated <i>Q</i><sub>inv</sub> and underestimated μ<sub>eff</sub>. The increase in effective channel width <i>W</i><sub>eff</sub> due to Δ<i>W</i> from shallow trench isolation (STI) top-corner rounding may compensate μ<sub>eff</sub> degradation due to STI stress. The tradeoff between μ<sub>eff</sub> and <i>W</i><sub>eff</sub> determines the impact of width scaling on <i>I</i><sub>DS</sub> and <i>Gm</i> . A new method based on the measured S-parameters, open-M1 deembedding, and Raphael simulation can precisely determine the mentioned parameters associated with the intrinsic channel and realize accurate extraction of μ<sub>eff</sub> in multifinger MOSFETs with various layouts and narrow widths down to 0.125 μm.

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