Experimental studies of the noise properties of a deep submicron CMOS process
暂无分享,去创建一个
Abstract Deep submicron CMOS technologies are presently very attractive for front-end electronics design, because of their features in terms of low power consumption, high integration density and radiation tolerance. A full understanding of the noise parameters of the devices belonging to these technologies is needed to confirm that they can be used to implement low-noise analog blocks. This paper describes a noise test system, which was purposely developed to measure the noise voltage spectrum of CMOS devices in a frequency range extending up to 100 MHz. As an application example, the results of the experimental characterization of the noise properties of a 0.35 μm CMOS process are presented.
[1] Sorin Cristoloveanu,et al. Noise contribution of the body resistance in partially-depleted SOI MOSFETs , 1998 .
[2] A.A. Abidi,et al. High-frequency noise measurements on FET's with small dimensions , 1986, IEEE Transactions on Electron Devices.