High Performance Embedded Dynamic Random Access Memory in Nano-Scale Technologies

Described are the high performance embedded DRAMs in nano-scale technology. The chapter starts with a discussion of the evolution of high-performance embedded DRAMs for the previous 15 years. It will then look into the principles of the embedded DRAMs, which include technology, macro and array architectures, mode of operations, wordline and bitline architectures, and sensing schemes. The discussion will also address ideas unique to the high-performance embedded DRAM such as Direct Write, Negative Wordline, Concurrent Refresh, Dataline Redundancy, BIST and Self-Repair methodology. After covering these key technical attributes, the chapter will detail the IBM embedded DRAM macros starting from ASIC to the most recent SOI embedded DRAM and the cache prototype designs for microprocessors. To conclude the chapter research, and development for future embedded DRAM with floating body cell, gain cell, and 3-dimensional embedded DRAM approach will be explored.

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