Fast RNS-based 2D-DCT computation on field-programmable devices

This paper shows the implementation of an 8/spl times/8 2D-DCT (discrete cosine transform) processor based on the residue number system (RNS). It makes use of a fast cosine transform (FCT) algorithm that requires a single multiplication stage for each signal path, while most other algorithms include paths with more than one multiplication. The row-column decomposition technique is used and each 1D-DCT processor requires only 14 multipliers and 32 adders and subtractors. The proposed RNS-based 2D-DCT processor provides a throughput improvement over the equivalent 2's complement system of up to 147% when 8-bit moduli are used. This is achieved due to the synergy between RNS and modern FPL device families.

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