Piecewise-Functional Broadside Tests Based on Reachable States
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[1] Irith Pomeranz,et al. On Complete Functional Broadside Tests for Transition Faults , 2008, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems.
[2] Kenneth M. Butler,et al. A case study of ir-drop in structured at-speed testing , 2003, International Test Conference, 2003. Proceedings. ITC 2003..
[3] Irith Pomeranz. Low-Power Test Generation by Merging of Functional Broadside Test Cubes , 2014, IEEE Transactions on Very Large Scale Integration (VLSI) Systems.
[4] Michael S. Hsiao,et al. A Study of Implication Based Pseudo Functional Testing , 2006, 2006 IEEE International Test Conference.
[5] Feng Lu,et al. Constraint extraction for pseudo-functional scan-based delay testing , 2005, Proceedings of the ASP-DAC 2005. Asia and South Pacific Design Automation Conference, 2005..
[6] Irith Pomeranz,et al. On generating pseudo-functional delay fault tests for scan designs , 2005, 20th IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems (DFT'05).
[7] Dong Xiang,et al. Scan Flip-Flop Grouping to Compress Test Data and Compact Test Responses for Launch-on-Capture Delay Testing , 2012, TODE.
[8] Irith Pomeranz. Generation of Functional Broadside Tests for Logic Blocks With Constrained Primary Input Sequences , 2013, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems.
[9] Irith Pomeranz,et al. On reset based functional broadside tests , 2010, 2010 Design, Automation & Test in Europe Conference & Exhibition (DATE 2010).
[10] Sudhakar M. Reddy,et al. At-speed scan test with low switching activity , 2010, 2010 28th VLSI Test Symposium (VTS).
[11] Sreejit Chakravarty,et al. An Approach to Minimizing Functional Constraints , 2006, 2006 21st IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems.
[12] Shlomi Sde-Paz,et al. Frequency and Power Correlation between At-Speed Scan and Functional Tests , 2008, 2008 IEEE International Test Conference.
[13] Irith Pomeranz. Functional broadside tests for embedded logic blocks , 2012, IET Comput. Digit. Tech..
[14] Irith Pomeranz,et al. Generation of Functional Broadside Tests for Transition Faults , 2006, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems.
[15] Jeff Rearick. Too much delay fault coverage is a bad thing , 2001, Proceedings International Test Conference 2001 (Cat. No.01CH37260).
[16] Irith Pomeranz. On the generation of scan-based test sets with reachable states for testing under functional operation conditions , 2004, Proceedings. 41st Design Automation Conference, 2004..
[17] Ilia Polian,et al. Functional Constraints vs. Test Compression in Scan-Based Delay Testing , 2006 .
[18] Irith Pomeranz. Signal-Transition Patterns of Functional Broadside Tests , 2013, IEEE Transactions on Computers.
[19] Irith Pomeranz,et al. Definition and generation of partially-functional broadside tests , 2009, IET Comput. Digit. Tech..