Design of a circuit-switched highly fault-tolerant k-ary n-cube

In this paper we present a strongly fault-tolerant design for the k-ary n-cube multiprocessor and examine its reconfigurability. Our design augments the k-ary n-cube with (/sup k///sub j/)/sup n/ spare nodes; each set of j/sup n/ regular nodes is connected to a spare node and the spare nodes are interconnected as a (/sup k///sub j/)-ary n-cube. Our approach utilizes the circuit-switched capabilities of the communication modules of the spare nodes to tolerate a large number of faulty nodes and faulty links without any performance degradation. Both theoretical and simulation results are presented.

[1]  Shantanu Dutt,et al.  Fast polylog-time reconfiguration of structurally fault-tolerant multiprocessors , 1993, Proceedings of 1993 5th IEEE Symposium on Parallel and Distributed Processing.

[2]  Jehoshua Bruck,et al.  Efficient fault-tolerant mesh and hypercube architectures , 1992, [1992] Digest of Papers. FTCS-22: The Twenty-Second International Symposium on Fault-Tolerant Computing.

[3]  Rami G. Melhem,et al.  Routing in Modular Fault-Tolerant Multiprocessor Systems , 1995, IEEE Trans. Parallel Distributed Syst..

[4]  C. Y. Lee.  An Algorithm for Path Connections and Its Applications , 1961, IRE Trans. Electron. Comput..

[5]  Schwetman.  Proceedings of the 1991 international conference on parallel processing , 1991 .

[6]  Jehoshua Bruck,et al.  Fault-tolerant meshes with small degree , 1993, SPAA '93.

[7]  Baback A. Izadi.  Design of fault-tolerant distributed memory multiprocessors , 1996 .

[8]  Adit D. Singh.  Interstitial Redundancy: An Area Efficient Fault Tolerance Scheme for Large Area VLSI Processor Arrays , 1988, IEEE Trans. Computers.