Binary decision diagrams in theory and practice
暂无分享,去创建一个
[1] Ted Stanion,et al. TSUNAMI: a path oriented scheme for algebraic test generation , 1991, [1991] Digest of Papers. Fault-Tolerant Computing: The Twenty-First International Symposium.
[2] Franc Brglez,et al. Design of experiments and evaluation of BDD ordering heuristics , 2001, International Journal on Software Tools for Technology Transfer.
[3] Oscar H. Ibarra,et al. Fast Approximation Algorithms for the Knapsack and Sum of Subset Problems , 1975, JACM.
[4] Shin-ichi Minato,et al. Fast factorization method for implicit cube set representation , 1996, IEEE Trans. Comput. Aided Des. Integr. Circuits Syst..
[5] Kenneth J. Supowit,et al. Finding the Optimal Variable Ordering for Binary Decision Diagrams , 1990, IEEE Trans. Computers.
[6] David R. O'Hallaron,et al. Space- and time-efficient BDD construction via working set control , 1998, Proceedings of 1998 Asia and South Pacific Design Automation Conference.
[7] Rolf Drechsler,et al. The K*BMD: A Verification Data Structure , 1997, IEEE Des. Test Comput..
[8] Beate Bollig,et al. On the Effect of Local Changes in the Variable Ordering of Ordered Decision Diagrams , 1996, Inf. Process. Lett..
[9] Randal E. Bryant,et al. Graph-Based Algorithms for Boolean Function Manipulation , 1986, IEEE Transactions on Computers.
[10] Masahiro Fujita,et al. On variable ordering of binary decision diagrams for the application of multi-level logic synthesis , 1991, Proceedings of the European Conference on Design Automation..
[11] Hiroshi Sawada,et al. Minimization of binary decision diagrams based on exchanges of variables , 1991, 1991 IEEE International Conference on Computer-Aided Design Digest of Technical Papers.
[12] Rolf Drechsler,et al. Dynamic minimization of word-level decision diagrams , 1998, Proceedings Design, Automation and Test in Europe.
[13] Shin-ichi Minato,et al. Zero-Suppressed BDDs for Set Manipulation in Combinatorial Problems , 1993, 30th ACM/IEEE Design Automation Conference.
[14] Detlef Sieling,et al. The Complexity of Minimizing FBDDs , 1999, MFCS.
[15] I. Wegener,et al. SIMULATED ANNEALING TO IMPROVE VARIABLE ORDERINGS FOR OBDDsBeate , 1995 .
[16] Olivier Coudert,et al. Two-level logic minimization: an overview , 1994, Integr..
[17] R. I. Bahar,et al. Algebraic decision diagrams and their applications , 1993, Proceedings of 1993 International Conference on Computer Aided Design (ICCAD).
[18] Jochen Bern,et al. Efficient OBDD-Based Boolean Manipulation in CAD Beyond Current Limits , 1995, 32nd Design Automation Conference.
[19] Masahiro Fujita,et al. Multi-Terminal Binary Decision Diagrams: An Efficient Data Structure for Matrix Representation , 1997, Formal Methods Syst. Des..
[20] Daniel Král. Algebraic and Uniqueness Properties of Parity Ordered Binary Decision Diagrams and their Generalization , 2000, Electron. Colloquium Comput. Complex..
[21] Fabio Somenzi,et al. Variable ordering and selection of FSM traversal , 1991, 1991 IEEE International Conference on Computer-Aided Design Digest of Technical Papers.
[22] Stefan Höreth. A word-level graph manipulation package , 2001, International Journal on Software Tools for Technology Transfer.
[23] Ingo Wegener,et al. Parity OBDDs Cannot be Handled Efficiently Enough , 1998, Inf. Process. Lett..
[24] E.M. Clarke,et al. Hybrid decision diagrams. Overcoming the limitations of MTBDDs and BMDs , 1995, Proceedings of IEEE International Conference on Computer Aided Design (ICCAD).
[25] Fabio Somenzi,et al. Logic synthesis and verification algorithms , 1996 .
[26] Beate Bollig,et al. Improving the Variable Ordering of OBDDs Is NP-Complete , 1996, IEEE Trans. Computers.
[27] Rolf Drechsler,et al. Linear transformations and exact minimization of BDDs , 1998, Proceedings of the 8th Great Lakes Symposium on VLSI (Cat. No.98TB100222).
[28] R. Bryant,et al. Verification of Arithmetic Functions with Binary Moment Diagrams , 1994 .
[29] Bernd Becker,et al. A BDD-based algorithm for computation of exact fault detection probabilities , 1993, FTCS-23 The Twenty-Third International Symposium on Fault-Tolerant Computing.
[30] Rolf Drechsler,et al. Efficient dynamic minimization of word-level DDs based on lower bound computation , 2000, Proceedings 2000 International Conference on Computer Design.
[31] Ingo Wegener,et al. Reduction of OBDDs in Linear Time , 1993, Inf. Process. Lett..
[32] Chikahiro Hori,et al. Interleaving based variable ordering methods for ordered binary decision diagrams , 1993, ICCAD.
[33] Beate Bollig,et al. Hierarchy Theorems for kOBDDs and kIBDDs , 1998, Theor. Comput. Sci..
[34] Sarma Vrudhula,et al. EVBDD-based algorithms for integer linear programming, spectral transformation, and function decomposition , 1994, IEEE Trans. Comput. Aided Des. Integr. Circuits Syst..
[35] Andreas Kuehlmann,et al. Formal verification of a PowerPC microprocessor , 1995, Proceedings of ICCD '95 International Conference on Computer Design. VLSI in Computers and Processors.
[36] Rolf Drechsler,et al. A genetic algorithm for variable ordering of obdds , 1996 .
[37] Harald Ruess,et al. An Efficient Decision Procedure for the Theory of Fixed-Sized Bit-Vectors , 1997, CAV.
[38] Bernd Becker,et al. Synthesis for Testability: Binary Decision Diagrams , 1992, Symposium on Theoretical Aspects of Computer Science.
[39] Rolf Drechsler,et al. The complexity of the inclusion operation on OFDD's , 1998, IEEE Trans. Comput. Aided Des. Integr. Circuits Syst..
[40] B. Krieger,et al. PLATO: A Tool for Computation of Exact Signal Probabilities , 1993, The Sixth International Conference on VLSI Design.
[41] Randal E. Bryant. Binary decision diagrams and beyond: enabling technologies for formal verification , 1995, ICCAD.
[42] Rolf Drechsler,et al. Synthesis for testability: circuits derived from ordered Kronecker functional decision diagrams , 1995, Proceedings the European Design and Test Conference. ED&TC 1995.
[43] Edmund M. Clarke,et al. Symbolic Model Checking: 10^20 States and Beyond , 1990, Inf. Comput..
[44] Sheldon B. Akers,et al. Binary Decision Diagrams , 1978, IEEE Transactions on Computers.
[45] Jayram S. Thathachar. On the Limitations of Ordered Representations of Functions , 1998, CAV 1998.
[46] Christoph Meinel,et al. A Unifying Theoretical Background for Some Bdd-based Data Structures , 1994, Formal Methods Syst. Des..
[47] David S. Johnson,et al. Computers and Intractability: A Guide to the Theory of NP-Completeness , 1978 .
[48] Shin-ichi Minato,et al. Zero-suppressed BDDs and their applications , 2001, International Journal on Software Tools for Technology Transfer.
[49] Bernard M. E. Moret,et al. Decision Trees and Diagrams , 1982, CSUR.
[50] M. R. Mercer,et al. Fast functional evaluation of candidate OBDD variable orderings , 1991, Proceedings of the European Conference on Design Automation..
[51] Prathima Agrawal,et al. Test Generation for Path Delay Faults Using Binary Decision Diagrams , 1995, IEEE Trans. Computers.
[52] Juraj Hromkovic,et al. Communication Complexity and Parallel Computing , 1997, Texts in Theoretical Computer Science An EATCS Series.
[53] Christoph Scholl,et al. Efficient ROBDD based computation of common decomposition functions of multi-output boolean functions , 1995 .
[54] Rolf Drechsler,et al. Fast exact minimization of BDDs , 1998, Proceedings 1998 Design and Automation Conference. 35th DAC. (Cat. No.98CH36175).
[55] Xudong Zhao,et al. Word Level Symbolic Model Checking: A New Approach for Verifying Arithmetic Circuits , 1995 .
[56] R. Drechsler,et al. Formal verification of word-level specifications , 1999, Design, Automation and Test in Europe Conference and Exhibition, 1999. Proceedings (Cat. No. PR00078).
[57] Randal E. Bryant,et al. Efficient implementation of a BDD package , 1991, DAC '90.
[58] Rolf Drechsler,et al. MORE: an alternative implementation of BDD packages by multi-operand synthesis , 1996, Proceedings EURO-DAC '96. European Design Automation Conference with EURO-VHDL '96 and Exhibition.
[59] Bernd Becker,et al. Fast OFDD based minimization of fixed polarity Reed-Muller expressions , 1994, EURO-DAC '94.
[60] Randal E. Bryant,et al. On the Complexity of VLSI Implementations and Graph Representations of Boolean Functions with Application to Integer Multiplication , 1991, IEEE Trans. Computers.
[61] Robert K. Brayton,et al. Logic Minimization Algorithms for VLSI Synthesis , 1984, The Kluwer International Series in Engineering and Computer Science.
[62] Rolf Drechsler,et al. Efficient Representation and Manipulation of Switching Functions Based on Ordered Kronecker Functional Decision Diagrams , 1994, 31st Design Automation Conference.
[63] Rolf Drechsler. Formal Verification of Circuits , 2000, Springer US.
[64] Ingo Wegener,et al. Graph Driven BDDs - A New Data Structure for Boolean Functions , 1995, Theor. Comput. Sci..
[65] Ingo Wegener,et al. Efficient algorithms for the transformation between different types of binary decision diagrams , 1997, Acta Informatica.
[66] I. Wegener. Branching Programs and Binary Deci-sion Diagrams-Theory and Applications , 1987 .
[67] 藤田 昌宏,et al. Evaluation and Improvements of Boolean Comparison Method Based on Binary Decision Diagrams , 1988 .
[68] R. Rudell. Dynamic variable ordering for ordered binary decision diagrams , 1993, Proceedings of 1993 International Conference on Computer Aided Design (ICCAD).
[69] Sarma B. K. Vrudhula,et al. BDD Based Decomposition of Logic Functions with Application to FPGA Synthesis , 1993, 30th ACM/IEEE Design Automation Conference.
[70] Bernd Becker,et al. Word-level decision diagrams, WLCDs and division , 1998, 1998 IEEE/ACM International Conference on Computer-Aided Design. Digest of Technical Papers (IEEE Cat. No.98CB36287).
[71] Christoph Meinel,et al. Mod-2-OBDDs—A data structure that generalizes EXOR-sum-of-products and ordered binary decision diagrams , 1996, Formal Methods Syst. Des..
[72] Matthias Krause. Untere Schranken für Berechnungen durch Verzweigungsprogramme , 1988 .
[73] Rolf Drechsler,et al. Manipulation of *BMDs , 1998, Proceedings of 1998 Asia and South Pacific Design Automation Conference.
[74] Alexander A. Razborov,et al. Lower Bounds for Deterministic and Nondeterministic Branching Programs , 1991, FCT.
[75] Don E. Ross,et al. Functional approaches to generating orderings for efficient symbolic representations , 1992, [1992] Proceedings 29th ACM/IEEE Design Automation Conference.
[76] Robert K. Brayton,et al. Implicit state enumeration of finite state machines using BDD's , 1990, 1990 IEEE International Conference on Computer-Aided Design. Digest of Technical Papers.
[77] Rolf Drechsler,et al. K*BMDs: a new data structure for verification , 1996, Proceedings ED&TC European Design and Test Conference.
[78] S. Minato. Binary Decision Diagrams and Applications for VLSI CAD , 1995 .
[79] Rolf Drechsler,et al. On the computational power of linearly transformed BDDs , 2000, Inf. Process. Lett..
[80] Kenneth L. McMillan,et al. Symbolic model checking , 1992 .
[81] S. Aborhey. Binary Decision Tree Test Functions , 1988, IEEE Trans. Computers.
[82] Jordan Gergov,et al. Time-Space Tradeoffs for Integer Multiplication on Various Types of Input Oblivious Sequential Machines , 1994, Inf. Process. Lett..
[83] Yung-Te Lai,et al. Edge-valued binary decision diagrams for multi-level hierarchical verification , 1992, DAC '92.
[84] Christoph Meinel,et al. Algorithms and Data Structures in VLSI Design: OBDD - Foundations and Applications , 2012 .
[85] Rolf Drechsler,et al. On the Relation between BDDs and FDDs , 1995, Inf. Comput..
[86] Sze-Tsen Hu. ON THE DECOMPOSITION OF SWITCHING FUNCTIONS , 1961 .
[87] Bernd Becker,et al. A hybrid fault simulator for synchronous sequential circuits , 1994, Proceedings., International Test Conference.
[88] Tae Sun Kim,et al. An Efficient Method for Optimal BDD Ordering Computation , 1993 .
[89] Albert R. Wang,et al. Logic verification using binary decision diagrams in a logic synthesis environment , 1988, [1988] IEEE International Conference on Computer-Aided Design (ICCAD-89) Digest of Technical Papers.
[90] Sharad Malik,et al. Application of BDDs in Boolean matching techniques for formal logic combinational verification , 2001, International Journal on Software Tools for Technology Transfer.
[91] Hiroyuki Ochi,et al. Breadth-first manipulation of very large binary-decision diagrams , 1993, Proceedings of 1993 International Conference on Computer Aided Design (ICCAD).
[92] Massoud Pedram,et al. Factored Edge-Valued Binary Decision Diagrams , 1997, Formal Methods Syst. Des..
[93] Randal E. Bryant,et al. Verification of arithmetic circuits using binary moment diagrams , 2001, International Journal on Software Tools for Technology Transfer.
[94] Ingo Wegener,et al. The Number of Knight's Tours Equals 33, 439, 123, 484, 294 - Counting with Binary Decision Diagrams , 1996, Electron. J. Comb..
[95] Beate Bollig,et al. Complexity Theoretical Aspects of OFDDs , 1996 .
[96] Eyal Kushilevitz,et al. Communication Complexity , 1997, Adv. Comput..
[97] Rolf Drechsler,et al. Minimization of free BDDs , 2002, Integr..
[98] Masahiro Fujita,et al. Evaluation and improvement of Boolean comparison method based on binary decision diagrams , 1988, [1988] IEEE International Conference on Computer-Aided Design (ICCAD-89) Digest of Technical Papers.
[99] Don E. Ross,et al. Heuristics to compute variable orderings for efficient manipulation of ordered binary decision diagrams , 1991, 28th ACM/IEEE Design Automation Conference.
[100] R. Drechsler,et al. On variable ordering and decomposition type choice in OKFDDs , 1995, Proceedings of ASP-DAC'95/CHDL'95/VLSI'95 with EDA Technofair.
[101] F. Somenzi,et al. Linear Sifting Of Decision Diagrams , 1997, Proceedings of the 34th Design Automation Conference.
[102] Christoph Meinel,et al. On the Complexity of Constructing Optimal Ordered Binary Decision Diagrams , 1994, MFCS.
[103] Kurt Keutzer,et al. Path-delay-fault testability properties of multiplexor-based networks , 1993, Integr..
[104] R. Bryant,et al. PHDD: an efficient graph representation for floating point circuit verification , 1997, ICCAD 1997.
[105] C. Y. Lee. Representation of switching circuits by binary-decision programs , 1959 .
[106] Rolf Drechsler,et al. On the Expressive Power of OKFDDs , 1997, Formal Methods Syst. Des..
[107] Fabio Somenzi,et al. Efficient manipulation of decision diagrams , 2001, International Journal on Software Tools for Technology Transfer.
[108] Wolfgang Rosenstiel,et al. Efficient graph-based computation and manipulation of functional decision diagrams , 1993, 1993 European Conference on Design Automation with the European Event in ASIC Design.
[109] Klaus Eckl,et al. Functional Multiple-Output Decomposition: Theory and an Implicit Algorithm , 1995, 32nd Design Automation Conference.
[110] Rolf Drechsler,et al. Binary Decision Diagrams - Theory and Implementation , 1998 .
[111] Shuzo Yajima,et al. The Complexity of the Optimal Variable Ordering Problems of Shared Binary Decision Diagrams , 1993, ISAAC.
[112] Jerry R. Burch,et al. Using bdds to verify multipliers , 1991, 28th ACM/IEEE Design Automation Conference.
[113] Rolf Drechsler. BiTeS: a BDD based test pattern generator for strong robust path delay faults , 1994, EURO-DAC '94.
[114] Hiroshi Imai,et al. A Reordering Operation for an Ordered Binary Decision Diagram and an Extended Framework for Combinatorics of Graphs , 1994, ISAAC.
[115] Ingo Wegener,et al. NC-Algorithms for Operations on Binary Decision Diagrams , 1993, Parallel Process. Lett..
[116] A. Kuehlmann,et al. Equivalence Checking Using Cuts And Heaps , 1997, Proceedings of the 34th Design Automation Conference.
[117] Jochen Bern,et al. Some heuristics for generating tree-like FBDD types , 1996, IEEE Trans. Comput. Aided Des. Integr. Circuits Syst..
[118] Ingo Wegener,et al. The complexity of Boolean functions , 1987 .
[119] S. Horeth. Compilation of optimized OBDD-algorithms , 1996, Proceedings EURO-DAC '96. European Design Automation Conference with EURO-VHDL '96 and Exhibition.
[120] Erik Meineche Schmidt,et al. The Complexity of Equivalence and Containment for Free Single Variable Program Schemes , 1978, ICALP.
[121] Wolfgang Rosenstiel,et al. Multilevel logic synthesis based on functional decision diagrams , 1992, [1992] Proceedings The European Conference on Design Automation.
[122] F. Somenzi,et al. Using lower bounds during dynamic BDD minimization , 2001 .
[123] Matthias Krause. Lower Bounds for Depth-Restricted Branching Programs , 1991, Inf. Comput..
[124] Rolf Drechsler,et al. Implementation of read-k-times BDDs on top of standard BDD packages , 2001, VLSI Design 2001. Fourteenth International Conference on VLSI Design.
[125] Hiroyuki Ochi,et al. Breadth-first manipulation of SBDD of boolean functions for vector processing , 1991, 28th ACM/IEEE Design Automation Conference.
[126] Rolf Drechsler,et al. Satisfiability Problems for OFDDs , 1996 .
[127] Jacob A. Abraham,et al. Indexed BDDs: Algorithmic Advances in Techniques to Represent and Verify Boolean Functions , 1997, IEEE Trans. Computers.
[128] Stephan Waack. On the Descriptive and Algorithmic Power of Parity Ordered Binary Decision Diagrams , 1997, STACS.
[129] Randal E. Bryant,et al. COSMOS: a compiled simulator for MOS circuits , 1987, DAC '87.
[130] Ingo Wegener,et al. A Comparison of Free BDDs and Transformed BDDs , 2001, Formal Methods Syst. Des..
[131] Detlef Sieling. The Nonapproximability of OBDD Minimization , 2002, Inf. Comput..
[132] Detlef Sieling. Lower Bounds for Linear Transformed OBDDs and FBDDs (Extende Abstract) , 1999, FSTTCS.