论文信息 - Design techniques for radiation hardened-phase locked loops

Design techniques for radiation hardened-phase locked loops

Abstract : Spacecraft experience radiation in the course of their operation and all the electronic equipment on-board these vehicles has to be designed to withstand the effects of this radiation. This thesis describes the effects of total ionization dose (TID) and single-event transients (SET) in phase-locked loops -- an important circuit block for communication circuits and clock generation. The design of a digital phase-locked loop made tolerant to SET through redundancy and error correction techniques is described. Digital phase-locked loops also can incorporate self-calibration techniques to compensate for the effects of TID. A linear analysis is presented for the design of digital phase-locked loops. This digital phase-locked loop was fabricated in the Honeywell 0.35 micrometer SOI CMOS process.

Anantha Nag Nemmani

[1] R.B. Staszewski,et al. All-digital phase-domain TX frequency synthesizer for Bluetooth radios in 0.13/spl mu/m CMOS , 2004, 2004 IEEE International Solid-State Circuits Conference (IEEE Cat. No.04CH37519).

[2] Kartikeya Mayaram,et al. Characterization of 1.2GHz Phase Locked Loops and Voltage Controlled Oscillators in a Total Dose Radiation Environment , 2005 .

[3] Jin-Sheng Wang,et al. A PVT tolerant 0.18MHz to 600MHz self-calibrated digital PLL in 90nm CMOS process , 2004, 2004 IEEE International Solid-State Circuits Conference (IEEE Cat. No.04CH37519).

[4] O. Musseau. Single-event effects in SOI technologies and devices , 1996 .

[5] Poras T. Balsara,et al. Just-in-time gain estimation of an RF digitally-controlled oscillator for digital direct frequency modulation , 2003 .

[6] M. Loretto,et al. Radiation damage in silicon , 1981 .

[7] A. Chandrakasan,et al. On-chip picosecond time measurement , 2000, 2000 Symposium on VLSI Circuits. Digest of Technical Papers (Cat. No.00CH37103).

[8] A. Leuciuc,et al. Single event transients characterization in SOI CMOS comparators , 2004, IEEE Transactions on Nuclear Science.

[9] Christer Svensson,et al. High-speed CMOS circuit technique , 1989 .

[10] Beomsup Kim,et al. A low-noise fast-lock phase-locked loop with adaptive bandwidth control , 2000, IEEE Journal of Solid-State Circuits.