A Real-time FPGA Implementation of a Barrel Distortion Correction Algorithm with Bilinear Interpolation

This paper presents a novel FPGA implementation of a barrel distortion correction algorithm with a focus on reducing hardware complexity. In order to perform real-time correction in hardware the undistorted output pixels must be produced in raster order. To do this the implementation uses the current scan position in the undistorted image to calculate which pixel in the distorted image to display. The magnification factor needed in this calculation is stored in a special look-up table that reduces the complexity of the hardware design, without significant loss of precision. The application of bilinear interpolation to improve the quality of the corrected image is also discussed and a real-time approach is presented. This approach uses a novel method of row buffering to compensate for data bandwidth constraints when trying to obtain the required pixels for interpolation.