FPGA-based architecture for high throughput, flexible and compact real-time GNSS software defined receiver

The advent of Galileo, along with the GPS and GLONASS modernizations, will make available a tremendous number of signals by 2015 to civilians for precise and reliable positioning. Nonetheless, the realtime integration of all those Global Navigation Satellite System (GNSS) signals remains a challenge and only a few solutions have been proposed yet. In this paper, a Field Programmable Gate Array (FPGA) based Software defined GNSS Receiver (SGR) is presented as a promising solution for fast real-time integration and as a perfect tool for Research and Development (R&D) in the field of navigation. The SGR is a compact L1 GPS C/A and Galileo hybrid receiver designed to incorporate up to 36 channels in the same FPGA. It has a sampling frequency of 60 MHz along with a maximal bandwidth of 24 MHz and it offers a real-time position solution updated at rates of at least 20 Hz. Yet, the receiver delivers centimetric position stability over short time periods and it demonstrates the capability to operate with signals Carrier-to-Noise-density ratios (C/N0) as low as 20 dB-Hz. First, a review of the SGR architecture is done in this paper. Then, resources evaluation and comparison with other available FPGA is achieved. Finally, real-time test results are presented and commented.