Translation of Intermediate Language to Timed Automata with Discrete Data
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[1] Thomas A. Henzinger,et al. HYTECH: a model checker for hybrid systems , 1997, International Journal on Software Tools for Technology Transfer.
[2] Wojciech Penczek,et al. Verics: A Tool for Verifying Timed Automata and Estelle Specifications , 2003, TACAS.
[3] Wojciech Penczek,et al. Checking Reachability Properties for Timed Automata via SAT , 2002, Fundam. Informaticae.
[4] Agata Janowska,et al. From Specification Languages to Timed Automata , 2002 .
[5] Edmund M. Clarke,et al. Design and Synthesis of Synchronization Skeletons Using Branching-Time Temporal Logic , 1981, Logic of Programs.
[6] Edmund M. Clarke,et al. Characterizing Finite Kripke Structures in Propositional Temporal Logic , 1988, Theor. Comput. Sci..
[7] Nicolas Halbwachs,et al. An implementation of three algorithms for timing verification based on automata emptiness , 1992, [1992] Proceedings Real-Time Systems Symposium.
[8] Agata Pólrola,et al. SAT-Based Reachability Checking for Timed Automata with Discrete Data , 2007, Fundam. Informaticae.