Impact of Scaling on Thermal Behavior of Silicon-on-Insulator Transistors

In this manuscript, the impact of scaling on self-heating of silicon-on-insulator (SOI) transistors is investigated. For the first time the effect of temperature dependent phonon-boundary scattering in silicon thin films, which results in reduction in thermal conduction in the channel region, is incorporated to the hydrodynamic simulation of electrons and holes in a commercial electro-thermal simulation tool. Results of DC electro-thermal simulations are used to study drain current degradation due to self-heating and to obtain the thermal resistance of SOI devices as a function of the gate length and silicon layer thickness. The device thermal resistance is increased by more than a factor of 2 due to the scaling of gate length from 180nm to 45nm. Neglecting phonon-boundary scattering in the channel region may underestimate the degradation of drain current due to self-heating by nearly a factor of two. Thermal resistance of SOI devices with 25nm silicon layer can be up to 8 times larger than that of bulk devices

[1]  M. Asheghi,et al.  Ballistic phonon transport in strained Si/SiGe nanostructures with an application to strained-silicon transistors , 2004, The Ninth Intersociety Conference on Thermal and Thermomechanical Phenomena In Electronic Systems (IEEE Cat. No.04CH37543).

[2]  Mehdi Asheghi,et al.  Impact of Thermal Sub-Continuum Effects on Electrical Performance of Silicon-on-Insulator Transistors , 2005 .

[3]  M. M. Pelella,et al.  Physical modeling of temperature dependences of SOI CMOS devices and circuits including self-heating , 1998 .

[4]  Mansun Chan,et al.  ESD reliability and protection schemes in SOI CMOS output buffers , 1995 .

[5]  Kenneth E. Goodson.  Thermal conduction in microelectronic circuits , 1993 .

[6]  M. G. Holland.  Analysis of Lattice Thermal Conductivity , 1963 .

[7]  Kenneth E. Goodson,et al.  Sub-Continuum Simulations of Heat Conduction in Silicon-on-Insulator Transistors , 1999, Heat Transfer: Volume 3.

[8]  M. Asheghi,et al.  Sub-continuum thermal analysis of strained-Si/SiGe transistor scaling , 2005, Semiconductor Thermal Measurement and Management IEEE Twenty First Annual IEEE Symposium, 2005..

[9]  P. Beckmann,et al.  The scattering of electromagnetic waves from rough surfaces , 1963 .

[10]  Mehdi Asheghi,et al.  Thermal Conductivity of Ultra Thin Single Crystal Silicon Layers: Part I — Experimental Measurements at Room and Cryogenic Temperatures , 2004 .

[11]  Mehdi Asheghi,et al.  Thermal Conductivity Measurements of Ultra-Thin Single Crystal Silicon Layers , 2006 .

[12]  James B. Kuo,et al.  Low-Voltage SOI CMOS VLSI Devices and Circuits , 2001 .

[13]  Zhiping Yu,et al.  An analytical drain current model considering both electron and lattice temperatures simultaneously for deep submicron ultrathin SOI NMOS devices with self-heating , 1995 .

[14]  Mehdi Asheghi,et al.  Phonon–boundary scattering in ultrathin single-crystal silicon layers , 2004 .

[15]  Sung-Mo Kang,et al.  EOS/ESD protection circuit design for deep submicron SOI technology , 1995, Electrical Overstress/Electrostatic Discharge Symposium Proceedings.

[16]  R.W. Dutton,et al.  Simulation of deep submicron SOI N-MOSFET considering the velocity overshoot effect , 1995, IEEE Electron Device Letters.

[17]  S. Polonsky,et al.  Time-resolved measurements of self-heating in SOI and strained-silicon MOSFETs using photon emission microscopy , 2004, IEEE Electron Device Letters.

[18]  J. Berthold,et al.  A 130-nm channel length partially depleted SOI CMOS-technology , 1999 .

[19]  T. Iwamatsu,et al.  Approaches to extra low voltage DRAM operation by SOI-DRAM , 1998 .

[20]  S. Laux,et al.  Monte-Carlo simulation of submicrometer Si n-MOSFETs at 77 and 300 K , 1988, IEEE Electron Device Letters.

[21]  V. Trivedi,et al.  Nanoscale FD/SOI CMOS: thick or thin BOX? , 2005, IEEE Electron Device Letters.

[22]  M. Asheghi,et al.  Ballistic phonon transport and self-heating effects in strained-silicon transistors , 2006, IEEE Transactions on Components and Packaging Technologies.

[23]  K. A. Jenkins,et al.  Impact of self-heating on digital SOI and strained-silicon CMOS circuits , 2003, 2003 IEEE International Conference on SOI.

[24]  Sadegh M. Sadeghipour,et al.  Modeling of Localized Heating Effect in Sub-Micron Silicon Transistors , 2003 .

[25]  A. O. Adan,et al.  SOI as a mainstream IC technology , 1998, 1998 IEEE International SOI Conference Proceedings (Cat No.98CH36199).

[26]  William Redman-White,et al.  Characterization of layout dependent thermal coupling in SOI CMOS current mirrors , 1996 .

[27]  Mehdi Asheghi,et al.  Thermal Transport in Novel Silicon Transistors , 2004 .

[28]  Thomas J. Watson,et al.  High Transconductance and Velocity Overshoot in NMOS Devices at the 0. l-pm Gate-Length Level , 1988 .

[29]  M. Sherony,et al.  Scalability of SOI technology into 0.13 /spl mu/m 1.2 V CMOS generation , 1998, International Electron Devices Meeting 1998. Technical Digest (Cat. No.98CH36217).

[30]  D. Flandre,et al.  Demonstration of the potential of accumulation-mode MOS transistors on SOI substrates for high-temperature operation (150-300 degrees C) , 1993, IEEE Electron Device Letters.

[31]  S. Wong,et al.  Temperature-Dependent Thermal Conductivity of Single-Crystal Silicon Layers in SOI Substrates , 1996, Microelectromechanical Systems (MEMS).

[32]  Mansun Chan,et al.  Threshold voltage model for deep-submicrometer fully depleted SOI MOSFET's , 1995 .

[33]  Kenneth E. Goodson,et al.  Heat Transfer Regimes in Microstructures , 1992 .

[34]  O. Faynot,et al.  A scalable SOI technology for three successive generations: 0.18, 0.13 and 0.1 /spl mu/m for low-voltage and low-power applications , 1996, 1996 IEEE International SOI Conference Proceedings.

[35]  Werner A. Rausch,et al.  Device and circuit design issues in SOI technology , 1999, Proceedings of the IEEE 1999 Custom Integrated Circuits Conference (Cat. No.99CH36327).

[36]  K. Blotekjaer.  Transport equations for electrons in two-valley semiconductors , 1970 .

[37]  D. Kern,et al.  High transconductance and velocity overshoot in NMOS devices at the 0.1- mu m gate-length level , 1988, IEEE Electron Device Letters.

[38]  D. Allen,et al.  Converting a 64 b PowerPC processor from CMOS bulk to SOI technology , 1999, Proceedings 1999 Design Automation Conference (Cat. No. 99CH36361).

[39]  W. Redman-White,et al.  Measurement and simulation of self-heating in SOI CMOS analogue circuits , 1997, 1997 IEEE International SOI Conference Proceedings.

[40]  Kouichi Kumagai,et al.  Design methodology for low power, high-speed CMOS devices utilizing SOI technology , 1993, Proceedings of 1993 IEEE International SOI Conference.

[41]  W. Redman-White,et al.  Characterisation of geometry dependence of SOI MOSFET thermal resistance and capacitance parameters , 1997, 1997 IEEE International SOI Conference Proceedings.

[42]  Mehdi Asheghi,et al.  Thermal conduction in ultrathin pure and doped single-crystal silicon layers at high temperatures , 2005 .

[43]  L. Wagner,et al.  Transient pass-transistor leakage current in SOI MOSFET's , 1997, IEEE Electron Device Letters.

[44]  Gang Chen,et al.  Thermal conductivity and ballistic-phonon transport in the cross-plane direction of superlattices , 1998 .

[45]  Jean-Pierre Colinge,et al.  Performances of low-voltage, low-power SOI CMOS technology , 1997, 1997 21st International Conference on Microelectronics. Proceedings.

[46]  Shaofeng Yu,et al.  Scalability revisited: 100 nm PD-SOI transistors and implications for 50 nm devices , 2000, 2000 Symposium on VLSI Technology. Digest of Technical Papers (Cat. No.00CH37104).