The statistics of NBTI-induced V/sub T/ and /spl beta/ mismatch shifts in pMOSFETs

Negative bias temperature instability (NBTI) is a pFET degradation mechanism that can result in threshold voltage shifts up to 100 mV or more, even in very thin oxide devices. Since analog circuits that utilize matched pairs of devices, such as current mirrors and differential pairs, generally depend on V/sub T/ matching considerably better than this, NBTI-induced V/sub T/ mismatch shift may represent a serious reliability concern for CMOS analog applications. Furthermore, induced /spl beta/ mismatch shift (affecting drain current level at a fixed gate overdrive voltage) may also impact drain current and transconductance mismatch. In this paper, experimental results of the statistics and scaling properties of NBTI-induced V/sub T/ and /spl beta/ mismatch shifts in saturation, and models describing these results, are presented.

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