Optimal static scheduling of real-time dependent tasks on reconfigurable hardware devices

Reconfigurable hardware devices are increasingly being adopted in the design of emerging complex embedded systems since they offer novel reconfiguration capabilities and a high density of heterogeneous resources conducting to improve the system performance. Key issues of designing such systems are interconnecting, memory management and task placement and scheduling. This paper addresses the problem of placement and scheduling of real-time DAG-structured applications in these emergent reconfigurable hardware devices. This paper presents a scheduling/placement methodology that uses mixed integer programming to establish the optimal static scenario for executing a set of periodic real-time inter-dependent tasks on reconfigurable devices. Experiments are conducted on a DAG composed of heterogeneous hardware tasks to evaluate the placement/scheduling quality. The results demonstrate a resource gain of 27 % achieved by the run-time reconfiguration concept compared to a static design. The configuration overhead is reduced to 1 % of the total running time. Due to pipelined scheduling, the task graph spanning is minimized by 4 % compared to sequential execution of the graph and the waiting time is reduced up to 7 % of the overall running time.

[1]  Miaoqing Huang,et al.  Hardware task scheduling optimizations for reconfigurable computing , 2008, 2008 Second International Workshop on High-Performance Reconfigurable Computing Technology and Applications.

[2]  Seda Ogrenci Memik,et al.  An ILP Formulation for the Task Graph Scheduling Problem Tailored to Bi-dimensional Reconfigurable Architectures , 2008, 2008 International Conference on Reconfigurable Computing and FPGAs.

[3]  Majid Sarrafzadeh,et al.  Fast Template Placement for Reconfigurable Computing Systems , 2000, IEEE Des. Test Comput..

[4]  Jürgen Teich,et al.  A new approach for on-line placement on reconfigurable devices , 2004, 18th International Parallel and Distributed Processing Symposium, 2004. Proceedings..

[5]  Jürgen Teich,et al.  Optimal FPGA module placement with temporal precedence constraints , 2001, Proceedings Design, Automation and Test in Europe. Conference and Exhibition 2001.

[6]  Goran Lj. Djordjevic,et al.  A Heuristic for Scheduling Task Graphs with Communication Delays Onto Multiprocessors , 1996, Parallel Comput..

[7]  Frode Eika Sandnes,et al.  Improved Static Multiprocessor Scheduling using Cyclic Task Graphs: A Genetic Approach , 1997, PARCO.

[8]  Oded Maler,et al.  Task graph scheduling using timed automata , 2003, Proceedings International Parallel and Distributed Processing Symposium.

[9]  Ikbel Belaid,et al.  New Three-Level Resource Management Enhancing Quality of Offline Hardware Task Placement on FPGA , 2010, Int. J. Reconfigurable Comput..

[10]  Xin Zhao,et al.  An ILP formulation for task mapping and scheduling on multi-core architectures , 2009, 2009 Design, Automation & Test in Europe Conference & Exhibition.

[11]  Carlos González,et al.  A Hardware Task-Graph Scheduler for Reconfigurable Multi-tasking Systems , 2008, 2008 International Conference on Reconfigurable Computing and FPGAs.