Efficient testing of hierarchical core-based SOCs

As chip design sizes continue to increase and they contain multiple instances of large and small cores, there is a need for a chip test architecture that allows efficient chip-level tests to be created while also reducing the memory and CPU time needed to create the tests. We define a hierarchical and core-based architecture for generating tests for cores and migrating them to the chip. This architecture allows testing multiple instances of the same core for the same cost as testing a single instance. The architecture also allows testing multiple instances of different cores as well. Memory use is kept low by generating tests for cores out of context and migrating them to the chip. We never have to build a full gate-level chip ATPG model. We show results of pattern count reduction possible when targeting multiple cores simultaneously.