RS-485 Communication Interface Chip With FPGA

In a master slave point to multipoint communication system, appropriate interface type and communication protocol are needed to realizd the information exchange between the master node and slave nodes. RS 485 interface is one of such standard interfaces satisfying this demand. When the master slave multipoint synchronous communication mode is chasen, the operation and frame format comply with HDLC/SDLC protocol. In this paper, an RS 485 communication interface chip based on HDLC/SDLC protocol is introduced, which is implemented in a single chip FPGA with VHDL language. The application result shows that the interface chip is of practical use because it has the characteristics of easy operation, small volume, low power consumption and high reliability.