论文信息 - Gate array placement based on mincut partitioning with path delay constraints

Gate array placement based on mincut partitioning with path delay constraints

Two placement methods for VLSI gate array layout considering interconnection delay are proposed. One is a fast iterative improvement algorithm, and the other is a simulated-annealing-based algorithm. Both the proposed methods directly treat timing constraints, each of which is given to a pair of pins in the circuit. Experimental results confirm the effectiveness of the proposed methods.<<ETX>>

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