On the effectiveness of residue code checking for parallel two's complement multipliers
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[1] Eiji Fujiwara,et al. Error-control coding for computer systems , 1989 .
[2] Torleiv Kløve,et al. Error detecting codes , 1995 .
[3] Christopher S. Wallace,et al. A Suggestion for a Fast Multiplier , 1964, IEEE Trans. Electron. Comput..
[4] E. E. Swartzlander,et al. Time redundant error correcting adders and multipliers , 1992, Proceedings 1992 IEEE International Workshop on Defect and Fault Tolerance in VLSI Systems.
[5] Bernard Courtois,et al. Strongly Code Disjoint Checkers , 1988, IEEE Trans. Computers.
[6] J.-C. Lo,et al. Concurrent error detection in arithmetic and logical operations using Berger codes , 1989, Proceedings of 9th Symposium on Computer Arithmetic.
[7] Uwe Sparmann,et al. On the check base selection problem for fast adders , 1993, Digest of Papers Eleventh Annual 1993 IEEE VLSI Test Symposium.
[8] Jill J. Hallenbeck,et al. Modulo 3 Residue Checker: New Results on Performance and Cost , 1988, IEEE Trans. Computers.
[9] Sudhakar M. Reddy,et al. On the effectiveness of residue code checking for parallel two's complement multipliers , 1996, IEEE Trans. Very Large Scale Integr. Syst..
[10] S. J. Piestrak. Self-testing checkers for arithmetic codes with any check base A , 1991, [1991] Proceedings Pacific Rim International Symposium on Fault Tolerant Systems.
[11] Stanislaw J. Piestrak,et al. Design of residue generators and multioperand modular adders using carry-save adders , 1991, [1991] Proceedings 10th IEEE Symposium on Computer Arithmetic.
[12] R. Heckelman,et al. Self-testing VLSI , 1981, 1981 IEEE International Solid-State Circuits Conference. Digest of Technical Papers.
[13] Israel Koren. Computer arithmetic algorithms , 1993 .
[14] J. Vuillemin,et al. Recursive implementation of optimal time VLSi integer multipliers , 1984 .
[15] Timothy J. Slegel,et al. Design and performance of the IBM Enterprise System/9000 Type 9121 Vector Facility , 1991, IBM J. Res. Dev..
[16] Thomas J. Brosnan,et al. Modular Error Detection for Bit-Serial Multiplication , 1988, IEEE Trans. Computers.
[17] D. Nikolos,et al. Efficient Design of Totally Self-Checking Checkers for all Low-Cost Arithmetic Codes , 1988, IEEE Trans. Computers.
[18] Jalil Fadavi-Ardekani,et al. M*N Booth encoded multiplier generator using optimized Wallace trees , 1992, Proceedings 1992 IEEE International Conference on Computer Design: VLSI in Computers & Processors.
[19] Otto Spaniol. Computer Arithmetic: Logic and Design , 1981 .
[20] Jack Sklansky,et al. Conditional-Sum Addition Logic , 1960, IRE Trans. Electron. Comput..
[21] P. H. Ang,et al. Generation of high speed CMOS multiplier-accumulators , 1988, Proceedings 1988 IEEE International Conference on Computer Design: VLSI.
[22] R. Stans. The testability of a modified Booth multiplier , 1989, [1989] Proceedings of the 1st European Test Conference.
[23] Shuzo Yajima,et al. An on-line error-detectable array divider with a redundant binary representation and a residue code , 1988, [1988] The Eighteenth International Symposium on Fault-Tolerant Computing. Digest of Papers.
[24] Stanislaw J. Piestrak. Design of High-Speed and Cost-Effective Self-Testing Checkers for Low-Cost Arithmetic Codes , 1990, IEEE Trans. Computers.
[25] Sudhakar M. Reddy,et al. On Totally Self-Checking Checkers for Separable Codes , 1977, IEEE Transactions on Computers.
[26] Algirdas Avizienis,et al. Arithmetic Error Codes: Cost and Effectiveness Studies for Application in Digital System Design , 1971, IEEE Transactions on Computers.
[27] Steffen Graf,et al. Error Detection Circuits , 1993 .
[28] Thammavarapu R. N. Rao,et al. Error coding for arithmetic processors , 1974 .
[29] Yoshihiro Tohma. Coding techniques in fault-tolerant, self-checking, and fail-safe circuits , 1986 .
[30] Orest J. Bedrij. Carry-Select Adder , 1962, IRE Trans. Electron. Comput..
[31] Shuzo Yajima,et al. On-Line Error-Detectable High-Speed Multiplier Using Redundant Binary Representation and Three-Rail Logic , 1987, IEEE Transactions on Computers.
[32] Kevin A. Kwiat,et al. Effective concurrent test for a parallel-input multiplier using modulo 3 , 1992, Digest of Papers. 1992 IEEE VLSI Test Symposium.
[33] Janak H. Patel,et al. Concurrent Error Detection in Multiply and Divide Arrays , 1983, IEEE Transactions on Computers.
[34] Michael Nicolaidis,et al. Efficient implementations of self-checking multiply and divide arrays , 1994, Proceedings of European Design and Test Conference EDAC-ETC-EUROASIC.
[35] Frederick F. Sellers,et al. Error detecting logic for digital computers , 1968 .
[36] Gordon Russell,et al. Advanced simulation and test methodologies for VLSI design , 1989 .
[37] Sudhakar M. Reddy,et al. Embedded totally self-checking checkers: a practical design , 1990, IEEE Design & Test of Computers.
[38] John J. Shedletsky. Comment on the Sequential and Indeterminate Behavior of an End-Around-Carry Adder , 1977, IEEE Trans. Computers.
[39] D. J. Kinniment,et al. Low-cost residue codes and their application to self-checking VLSI systems , 1985 .
[40] Bruce A. Wooley,et al. A Two's Complement Parallel Array Multiplication Algorithm , 1973, IEEE Transactions on Computers.
[41] John F. Wakerly,et al. Error detecting codes, self-checking circuits and applications , 1978 .
[42] D. Zuras,et al. Balanced delay trees and combinatorial division in VLSI , 1986 .
[43] Glen G. Langdon,et al. Concurrent error detection for group look-ahead binary adders , 1970 .
[44] Belle W. Y. Wei,et al. Area-Time Optimal Adder Design , 1990, IEEE Trans. Computers.
[45] Michael Nicolaidis,et al. Efficient implementations of self-checking adders and ALUs , 1993, FTCS-23 The Twenty-Third International Symposium on Fault-Tolerant Computing.