Method and device for controlling internal power supply voltage generating circuit in semiconductor memory device

An integrated circuit memory device includes a plurality of banks of a memory array and a power line connected to the plurality of banks. A plurality of internal voltage generating circuits are connected in parallel to the power line and are configured to provide internal voltage to the plurality of banks. A control circuit is connected to the plurality of internal voltage generating circuits and is configured to provided the internal voltage to more than one of the plurality of banks during a requested operation performed by fewer than all of the plurality of banks.