A real-time 256*256 point two-dimensional FFT single-chip processor
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A single-chip 400-MFLOPS 2-D FFT processor VLSI architecture designed using 0.8- mu m CMOS technology is proposed. This processor integrates 380000 transistors in an area of 11.58*11.58 mm/sup 2/ with a typical machine cycle time of 25 ns. The 24-bit floating point processor executes 2/sup n/*2/sup n/ point 2-D FFT in real time, e.g., 256*256 point FFT is executed in 14 ms. This excellent performance in terms of speed and dynamic range makes the real-time processing practical for video as well as speech processing.<<ETX>>
[1] Ikuo Harada,et al. CHAMP: Chip Floor Plan for Hierarchical VLSI Layout Design , 1985, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems.
[2] H. Kitazawa. A Look-Ahead Line Search Algorithm with High Wireability for Custom VLSI Design , 1985 .
[3] M. Araki,et al. A 32b floating point CMOS digital signal processor , 1986, 1986 IEEE International Solid-State Circuits Conference. Digest of Technical Papers.