Equalization of multi-Gb/s chip-to-chip interconnects affected by manufacturing tolerances

Abstract Electrical chip-to-chip interconnects suffer from considerable intersymbol interference at multi-Gb/s data rates, due to the frequency-dependent attenuation. Hence, reliable communication at high data rates requires equalization, to compensate for the channel response. As these interconnects are prone to manufacturing tolerances, the equalizer must be adjusted to each specific channel realization to perform optimally. We adopt a reduced-complexity equalization scheme where (part of) the equalizer is fixed, by involving the channel statistics into the equalizer derivation. For a 10 cm on-board microstrip interconnect with a 10% tolerance on its parameters, we point out that 2-PAM transmission using a fixed prefilter and an adjustable feedback filter, both with few taps, yields only a moderate bit error rate degradation, compared to the all-adjustable equalizer; at a bit error rate of 10 − 12 , these degradations are about 1.1  dB and 3  dB, when operating at 20 Gb/s and 80 Gb/s, respectively.

[1]  Marc Moeneclaey,et al.  Performance analysis of pre-equalized multilevel partial response schemes , 2015, 2015 IEEE International Symposium on Signal Processing and Information Technology (ISSPIT).

[2]  Jae-Yoon Sim,et al.  An 8GB/s quad-skew-cancelling parallel transceiver in 90nm CMOS for high-speed DRAM interface , 2012, 2012 IEEE International Solid-State Circuits Conference.

[3]  Guy Torfs,et al.  A Wide-Band, 5-Tap Transversal Filter With Improved Testability for Equalization up to 84 Gb/s , 2015, IEEE Microwave and Wireless Components Letters.

[4]  Xiaoxiong Gu,et al.  Is 25 Gb/s On-Board Signaling Viable? , 2009, IEEE Transactions on Advanced Packaging.

[5]  Antonio Orlandi,et al.  Design and modeling for chip-to-chip communication at 20 Gbps , 2010, 2010 IEEE International Symposium on Electromagnetic Compatibility.

[6]  Thomas Toifl,et al.  A 10 Gb/s 8-Tap 6b 2-PAM/4-PAM Tomlinson–Harashima Precoding Transmitter for Future Memory-Link Applications in 22-nm SOI CMOS , 2013, IEEE Journal of Solid-State Circuits.

[7]  Thomas Toifl,et al.  A 28-Gb/s 4-Tap FFE/15-Tap DFE Serial Link Transceiver in 32-nm SOI CMOS Technology , 2012, IEEE Journal of Solid-State Circuits.

[8]  Dries Vande Ginste,et al.  Generalized Decoupled Polynomial Chaos for Nonlinear Circuits With Many Random Parameters , 2015, IEEE Microwave and Wireless Components Letters.

[9]  Cong Gao,et al.  The Generalized ICN for 25Gbps+ channel using NRZ, PAM-M or Duobinary coding scheme , 2012, 2012 IEEE International Symposium on Electromagnetic Compatibility.

[10]  Marc Moeneclaey,et al.  MMSE equalization of multi-Gb/s chip-to-chip interconnects with M-PAM signaling affected by manufacturing tolerances , 2016, 2016 Symposium on Communications and Vehicular Technologies (SCVT).

[11]  S. Gowda,et al.  A 10-Gb/s 5-Tap DFE/4-Tap FFE Transceiver in 90-nm CMOS Technology , 2006, IEEE Journal of Solid-State Circuits.

[12]  Vladimir Stojanovic,et al.  Modeling and analysis of high-speed links , 2003, Proceedings of the IEEE 2003 Custom Integrated Circuits Conference, 2003..

[13]  Goichi Ono,et al.  A 12.3-mW 12.5-Gb/s Complete Transceiver in 65-nm CMOS Process , 2010, IEEE Journal of Solid-State Circuits.

[14]  Gerhard P. Fettweis,et al.  The Tactile Internet: Applications and Challenges , 2014, IEEE Vehicular Technology Magazine.

[15]  Azita Emami-Neyestanak,et al.  A 15-Gb/s 0.5-mW/Gbps Two-Tap DFE Receiver With Far-End Crosstalk Cancellation , 2011, IEEE Journal of Solid-State Circuits.

[16]  Dries Vande Ginste,et al.  An Effective Modeling Framework for the Analysis of Interconnects Subject to Line-Edge Roughness , 2015, IEEE Microwave and Wireless Components Letters.

[17]  T. Dhaene,et al.  Stochastic Modeling-Based Variability Analysis of On-Chip Interconnects , 2012, IEEE Transactions on Components, Packaging and Manufacturing Technology.