Distributed computing and the multicore revolution

Changes in technology can have far-reaching effects on theory. For example, while Turing's work on computability predated the first electronic computers, complexity theory flowered only after computers became a reality. After all, an algorithm's complexity may not matter much in a mathematics journal, but matters quite a bit in a FORTRAN program. We argue that something similar is going on with parallel and concurrent computation: after decades of being respected but not taken seriously, research on multiprocessor algorithms and data structures is going mainstream.

[1]  David A. Wood,et al.  LogTM: log-based transactional memory , 2006, The Twelfth International Symposium on High-Performance Computer Architecture, 2006..

[2]  Maurice Herlihy,et al.  Obstruction-free synchronization: double-ended queues as an example , 2003, 23rd International Conference on Distributed Computing Systems, 2003. Proceedings..

[3]  Mark Moir,et al.  Formal Verification of a Lazy Concurrent List-Based Set Algorithm , 2006, CAV.

[4]  Maurice Herlihy,et al.  Wait-free synchronization , 1991, TOPL.

[5]  Ramesh Subramonian,et al.  LogP: towards a realistic model of parallel computation , 1993, PPOPP '93.

[6]  Dan Grossman,et al.  What do high-level memory models mean for transactions? , 2006, MSPC '06.

[7]  Marcos K. Aguilera,et al.  Abortable and query-abortable objects and their efficient implementation , 2007, PODC '07.

[8]  Rajeev Alur,et al.  Contention-Free Complexity of Shared Memory Algorithms , 1996, Inf. Comput..

[9]  Maurice Herlihy,et al.  Transactional Memory: Architectural Support For Lock-free Data Structures , 1993, Proceedings of the 20th Annual International Symposium on Computer Architecture.

[10]  Michael L. Scott.  Sequential Specification of Transactional Memory Semantics , 2006 .

[11]  Andreas Reuter,et al.  Transaction Processing: Concepts and Techniques , 1992 .

[12]  Marc Tremblay,et al.  A Third-Generation 65nm 16-Core 32-Thread Plus 32-Scout-Thread CMT SPARC® Processor , 2008, 2008 IEEE International Solid-State Circuits Conference - Digest of Technical Papers.

[13]  Jan Vitek,et al.  STMBench7: a benchmark for software transactional memory , 2007, EuroSys '07.

[14]  Mark Moir,et al.  Obstruction-Free Step Complexity: Lock-Free DCAS as an Example , 2005, DISC.

[15]  Steven Fortune,et al.  Parallelism in random access machines , 1978, STOC.

[16]  Keir Fraser,et al.  Language support for lightweight transactions , 2003, SIGP.

[17]  Nir Shavit,et al.  Split-ordered lists: lock-free extensible hash tables , 2003, PODC '03.

[18]  Michael M. Swift,et al.  Pathological Interaction of Locks with Transactional Memory , 2008 .

[19]  Maurice Herlihy,et al.  Software transactional memory for dynamic-sized data structures , 2003, PODC '03.

[20]  Cong Wang,et al.  NZTM: nonblocking zero-indirection transactional memory , 2009, SPAA '09.

[21]  A. McDonald,et al.  Architectural Semantics for Practical Transactional Memory , 2006, ISCA 2006.

[22]  Craig Zilles,et al.  Extending Hardware Transactional Memory to Support Non-busy Waiting and Non-transactional Actions , 2006 .

[23]  Emmett Witchel,et al.  The Linux Kernel: A Challenging Workload for Transactional Memory , 2006 .

[24]  C. Greg Plaxton,et al.  Thread Scheduling for Multiprogrammed Multiprocessors , 1998, SPAA '98.

[25]  Mark D. Hill,et al.  Thread-Level Transactional Memory , 2005 .

[26]  Mark Moir,et al.  Integrating Transactional Memory into C , 2007 .

[27]  Amos Israeli,et al.  Disjoint-access-parallel implementations of strong shared memory primitives , 1994, PODC '94.

[28]  Rachid Guerraoui,et al.  Synchronizing without locks is inherently expensive , 2006, PODC '06.

[29]  Nancy A. Lynch,et al.  Memory consistency models for high-performance distributed computing , 2001 .

[30]  Bradley C. Kuszmaul,et al.  Unbounded Transactional Memory , 2005, HPCA.

[31]  Nir Shavit,et al.  Software transactional memory , 1995, PODC '95.

[32]  Rachid Guerraoui,et al.  Toward a theory of transactional contention managers , 2005, PODC '05.

[33]  Amir Pnueli,et al.  Verifying Correctness of Transactional Memories , 2007 .

[34]  Kunle Olukotun,et al.  Transactional memory coherence and consistency , 2004, Proceedings. 31st Annual International Symposium on Computer Architecture, 2004..

[35]  Amir Pnueli,et al.  Verification of Transactional Memories that Support Non-Transactional Memory Accesses , 2008 .

[36]  Timothy L. Harris,et al.  A Pragmatic Implementation of Non-blocking Linked-Lists , 2001, DISC.

[37]  Milo M. K. Martin,et al.  Subtleties of transactional memory atomicity semantics , 2006, IEEE Computer Architecture Letters.

[38]  Maurice Herlihy,et al.  Transactional boosting: a methodology for highly-concurrent transactional objects , 2008, PPoPP.

[39]  Maged M. Michael,et al.  Nonblocking Algorithms and Preemption-Safe Locking on Multiprogrammed Shared Memory Multiprocessors , 1998, J. Parallel Distributed Comput..

[40]  Leslie G. Valiant,et al.  A bridging model for parallel computation , 1990, CACM.

[41]  Simon L. Peyton Jones,et al.  Composable memory transactions , 2005, CACM.

[42]  Mark Moir,et al.  Hybrid transactional memory , 2006, ASPLOS XII.

[43]  Mateo Valero Cortés,et al.  Hybrid transactional memory to accelerate safe lock-based transactions , 2008 .

[44]  Mark Moir.  Practical implementations of non-blocking synchronization primitives , 1997, PODC '97.

[45]  Maurice Herlihy,et al.  Robust Contention Management in Software Transactional Memory , 2005, OOPSLA 2005.

[46]  Virendra J. Marathe,et al.  Adaptive Software Transactional Memory , 2005, DISC.

[47]  Marc Tremblay.  Transactional memory for a modern microprocessor , 2007, PODC '07.

[48]  Dan Grossman,et al.  High-level small-step operational semantics for transactions , 2008, POPL '08.

[49]  Sarita V. Adve,et al.  Shared Memory Consistency Models: A Tutorial , 1996, Computer.

[50]  Bratin Saha,et al.  McRT-STM: a high performance software transactional memory system for a multi-core runtime , 2006, PPoPP '06.

[51]  Mark Moir,et al.  Using elimination to implement scalable and lock-free FIFO queues , 2005, SPAA '05.

[52]  Mark Moir,et al.  PhTM: Phased Transactional Memory , 2007 .

[53]  Craig B. Zilles,et al.  An Analysis of I/O And Syscalls In Critical Sections And Their Implications For Transactional Memory , 2008, ISPASS 2008 - IEEE International Symposium on Performance Analysis of Systems and software.

[54]  William N. Scherer,et al.  Advanced contention management for dynamic software transactional memory , 2005, PODC '05.