A CMOS magnetic field sensor array that can be implemented along with analog and digital signal processing circuitry in the form of a single integrated circuit for instrumentation or measurement is discussed. The design realizes a single sensor device through interconnection of a few n-channel magnetic-field-sensitive MOSFETs (MAGFETs) in one circuit. The experimental measurements suggest that the interconnection, which forms a parallel tree structure, provides a higher relative sensitivity compared to that of the genealogical tree structure reported previously. The parallel structure eliminates the additional power supply and body effects and takes less integration area. The relative sensitivity of the CMOS sensor device with an array of five split-drain MAGFETs is 77 mA/A/T. >
[1]
R. Popovic,et al.
Magnetotransistor in CMOS technology
,
1986,
IEEE Transactions on Electron Devices.
[2]
S. Kordic.
Integrated 3-D Magnetic sensor based on an n-p-n transistor
,
1986,
IEEE Electron Device Letters.
[3]
A. Nathan,et al.
Two-dimensional numerical modeling of magnetic-field sensors in CMOS technology
,
1985,
IEEE Transactions on Electron Devices.
[4]
T. R. Viswanathan,et al.
A novel high gain MOS magnetic field sensor
,
1986
.
[5]
P. W. Fry,et al.
A silicon MOS magnetic field transducer of high sensitivity
,
1969
.
[6]
R.S. Popovic,et al.
A CMOS magnetic field sensor
,
1983,
IEEE Journal of Solid-State Circuits.