Compiling Verilog into timed finite state machines
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[1] Felice Balarin,et al. Verilog HDL Modeling Styles for Formal Verification , 1993, CHDL.
[2] Sérgio Vale Aguiar Campos,et al. Symbolic Model Checking , 1993, CAV.
[3] Daniel D. Gajski,et al. Design Methodology for High-Level Synthesis , 1992 .
[4] Minh N. Do,et al. Youn-Long Steve Lin , 1992 .
[5] Alfred V. Aho,et al. Compilers: Principles, Techniques, and Tools , 1986, Addison-Wesley series in computer science / World student series edition.
[6] Szu-Tsung Cheng,et al. HSIS: A BDD-Based Environment for Formal Verification , 1994, 31st Design Automation Conference.
[7] Donald E. Thomas,et al. The Verilog® Hardware Description Language , 1990 .
[8] Szu-Tsung Cheng,et al. Compiling Verilog into Automata , 1994 .
[9] Charles N. Fischer,et al. Crafting a Compiler , 1988 .