Enhancing BIST based single/multiple stuck-at fault diagnosis by ambiguous test set

We have proposed a method for identifying candidate single stuck-at faults based on the ambiguous test set (Takahashi et al., 2003). In this paper, we propose enhancing methods for diagnosing single/multiple stuck-at faults under BIST environment to reduce the number of candidate faults. The enhancing method uses the number of detections for candidate faults and the first detecting test to diagnose the candidate faults. Moreover, we propose an enhancing method for diagnosing multiple stuck-at faults by using test-pairs.

[1]  Hiroshi Takahashi,et al.  On diagnosing multiple stuck-at faults using multiple and singlefault simulation in combinational circuits , 2002, IEEE Trans. Comput. Aided Des. Integr. Circuits Syst..

[2]  Hiroshi Takahashi,et al.  Multiple fault diagnosis by sensitizing input pairs , 1995, IEEE Design & Test of Computers.

[3]  Jacob Savir,et al.  Identification of failing tests with cycling registers , 1988, International Test Conference 1988 Proceeding@m_New Frontiers in Testing.

[4]  J. G-Dastidar.  Fault diagnosis in scan-based bist using both time and space information , 1999 .

[5]  Melvin A. Breuer,et al.  Digital systems testing and testable design , 1990 .

[6]  Saman Adham,et al.  BIST fault diagnosis in scan-based VLSI environments , 1996, Proceedings International Test Conference 1996. Test and Design Validity.

[7]  Alex Orailoglu,et al.  Improved fault diagnosis in scan-based BIST via superposition , 2000, Proceedings 37th Design Automation Conference.

[8]  Vinod K. Agarwal,et al.  A diagnosis method using pseudo-random vectors without intermediate signatures , 1989, 1989 IEEE International Conference on Computer-Aided Design. Digest of Technical Papers.

[9]  Janusz Rajski,et al.  Fault diagnosis in scan-based BIST , 1997, Proceedings International Test Conference 1997.

[10]  Malgorzata Marek-Sadowska,et al.  An efficient and effective methodology on the multiple fault diagnosis , 2003, International Test Conference, 2003. Proceedings. ITC 2003..

[11]  J.A. Waicukauski,et al.  Failure diagnosis of structured VLSI , 1989, IEEE Design & Test of Computers.

[12]  Janusz Rajski,et al.  Diagnosis of Scan Cells in BIST Environment , 1999, IEEE Trans. Computers.

[13]  Saman Adham,et al.  Scan-based BIST fault diagnosis , 1999, IEEE Trans. Comput. Aided Des. Integr. Circuits Syst..

[14]  M. Ray Mercer,et al.  Using logic models to predict the detection behavior of statistical timing defects , 2003, International Test Conference, 2003. Proceedings. ITC 2003..

[15]  H. Takahashi.  BIST Based Diagnosis Using Ambiguous Test Set , 2003 .

[16]  Alex Orailoglu,et al.  Deterministic partitioning techniques for fault diagnosis in scan-based BIST , 2000, Proceedings International Test Conference 2000 (IEEE Cat. No.00CH37159).

[17]  Yuzo Takamatsu,et al.  BIST based fault diagnosis using ambiguous test set , 2003, Proceedings 18th IEEE Symposium on Defect and Fault Tolerance in VLSI Systems.