SUBTRACT: a program for the efficient evaluation of substrate parasitics in integrated circuits

Algorithms for the efficient evaluation of substrate parasitics in mixed-signal integrated circuits have been developed and incorporated in an extraction tool for substrate parasitics, SUBTRACT. Using a preprocessed, polynomial-based boundary element method, SUBTRACT enables the parasitic extraction process to be completely technology independent, allowing for fast evaluation. Additionally, techniques to accelerate the iterative solution of the resulting impedance matrix have been developed and employed to further improve the speed advantages that this method offers. The preprocessed boundary element method is more efficient than finite-difference schemes and orders of magnitude faster than general boundary element methods using a direct evaluation of Green's function. Results of employing SUBTRACT to the design and verification of a mixed-signal A/D converter IC are described.

[1]  Jacob K. White,et al.  FastCap: a multipole accelerated 3-D capacitance extraction program , 1991, IEEE Trans. Comput. Aided Des. Integr. Circuits Syst..

[2]  L. Greengard The Rapid Evaluation of Potential Fields in Particle Systems , 1988 .

[3]  Y. Saad,et al.  GMRES: a generalized minimal residual algorithm for solving nonsymmetric linear systems , 1986 .

[4]  David J. Allstot,et al.  Fast parasitic extraction for substrate coupling in mixed-signal ICs , 1995, Proceedings of the IEEE 1995 Custom Integrated Circuits Conference.

[5]  N. P. van der Meijs,et al.  Boundary element methods for 3D capacitance and substrate resistance calculations in inhomogeneous media in a VLSI layout verification package , 1994 .

[6]  Maher Kayal,et al.  LAYIN: toward a global solution for parasitic coupling modeling and visualization , 1994, Proceedings of IEEE Custom Integrated Circuits Conference - CICC '94.

[7]  Shoichi Masui,et al.  Experimental results and modeling techniques for substrate noise in mixed-signal integrated circuits , 1993 .

[8]  V. Rokhlin Rapid solution of integral equations of classical potential theory , 1985 .

[9]  Wen Wang,et al.  Chip Substrate Resistance Modeling Technique for Integrated Circuit Design , 1984, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems.

[10]  D. J. Allstot,et al.  Rapid simulation of substrate coupling effects in mixed-mode ICs , 1993, Proceedings of IEEE Custom Integrated Circuits Conference - CICC '93.

[11]  L. D. Smith,et al.  A 27MHz Mixed Analog/digital Magnetic Recording Channel DSP Using Partial Response Signalling With Maximum Likelihood Detection , 1991, 1991 IEEE International Solid-State Circuits Conference. Digest of Technical Papers.

[12]  Robert G. Meyer,et al.  Modeling and analysis of substrate coupling in integrated circuits , 1996 .

[13]  Robert G. Meyer,et al.  Modeling and analysis of substrate coupling in integrated circuits , 1995, Proceedings of the IEEE 1995 Custom Integrated Circuits Conference.