Performance of rate 0.96 (68254, 65536) EG-LDPC code for NAND Flash memory error correction
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[1] Tong Zhang,et al. Estimating Information-Theoretical nand Flash Memory Storage Capacity and its Implication to Memory System Design Space Exploration , 2012, IEEE Transactions on Very Large Scale Integration (VLSI) Systems.
[2] A. Visconti,et al. Random Telegraph Noise Effect on the Programmed Threshold-Voltage Distribution of Flash Memories , 2009, IEEE Electron Device Letters.
[3] Kenneth Rose,et al. Design of on-chip error correction systems for multilevel NOR and NAND flash memories , 2007, IET Circuits Devices Syst..
[4] Robert G. Gallager,et al. Low-density parity-check codes , 1962, IRE Trans. Inf. Theory.
[5] D.J.C. MacKay,et al. Good error-correcting codes based on very sparse matrices , 1997, Proceedings of IEEE International Symposium on Information Theory.
[6] K. Prall. Scaling Non-Volatile Memory Below 30nm , 2007, 2007 22nd IEEE Non-Volatile Semiconductor Memory Workshop.
[7] Rüdiger L. Urbanke,et al. The capacity of low-density parity-check codes under message-passing decoding , 2001, IEEE Trans. Inf. Theory.
[8] Shu Lin,et al. Codes on finite geometries , 2005, IEEE Transactions on Information Theory.
[9] Luca Crippa,et al. A 4Gb 2b/cell NAND Flash Memory with Embedded 5b BCH ECC for 36MB/s System Read Throughput , 2006, 2006 IEEE International Solid State Circuits Conference - Digest of Technical Papers.
[10] Tong Zhang,et al. Using Data Postcompensation and Predistortion to Tolerate Cell-to-Cell Interference in MLC nand Flash Memory , 2010, IEEE Transactions on Circuits and Systems I: Regular Papers.
[11] Jungdal Choi,et al. Effects of floating-gate interference on NAND flash memory cell operation , 2002 .
[12] Tong Zhang,et al. On the Use of Soft-Decision Error-Correction Codes in nand Flash Memory , 2011, IEEE Transactions on Circuits and Systems I: Regular Papers.
[13] Wei Liu,et al. Low-Power High-Throughput BCH Error Correction VLSI Design for Multi-Level Cell NAND Flash Memories , 2006, 2006 IEEE Workshop on Signal Processing Systems Design and Implementation.
[14] Sung-Soo Lee,et al. A 7MB/s 64Gb 3-bit/cell DDR NAND flash memory in 20nm-node technology , 2011, 2011 IEEE International Solid-State Circuits Conference.
[15] Qiuju Diao,et al. Cyclic and Quasi-Cyclic LDPC Codes on Row and Column Constrained Parity-Check Matrices and Their Trapping Sets , 2010, ArXiv.
[16] Jin-Ki Kim,et al. A 3.3 V 32 Mb NAND flash memory with incremental step pulse programming scheme , 1995, Proceedings ISSCC '95 - International Solid-State Circuits Conference.
[17] Shu Lin,et al. Low-density parity-check codes based on finite geometries: A rediscovery and new results , 2001, IEEE Trans. Inf. Theory.