A 10Gb/s CMOS CDR and DEMUX IC with a Quarter-Rate Linear Phase Detector

A 10Gb/s CDR and DEMUX IC in a 0.13mum CMOS consumes 100mA from a 1.2V core supply and 205mA from a 2.5V I/O supply including 18 LVDS drivers. The CDR system uses a quarter-rate linear phase detector and a 4-phase 2.5GHz LC-QVCO to achieve a BER of <10-15 and a jitter tolerance of 0.5UIpp exceeding the OC-192 standard

[1]  Michael M. Green,et al.  OC-192 transmitter and receiver in standard 0.18-μm CMOS , 2002, IEEE J. Solid State Circuits.

[2]  Deog-Kyoon Jeong,et al.  A 2.5-10Gb/s CMOS transceiver with alternating edge sampling phase detection for loop characteristic stabilization , 2003, 2003 IEEE International Solid-State Circuits Conference, 2003. Digest of Technical Papers. ISSCC..

[3]  C.R. Hogge A self correcting clock recovery circuit , 1985, IEEE Transactions on Electron Devices.

[4]  C.S.G. Conroy,et al.  A four-channel 3.125-Gb/s/ch CMOS serial-link transceiver with a mixed-mode adaptive equalizer , 2005, IEEE Journal of Solid-State Circuits.

[5]  C. Zimmermann,et al.  A 10-gb/s CMOS clock and data recovery circuit with an analog phase interpolator , 2005, IEEE Journal of Solid-State Circuits.

[6]  A. Bonfanti,et al.  Analysis and design of a 1.8-GHz CMOS LC quadrature VCO , 2002, IEEE J. Solid State Circuits.

[7]  B. Razavi,et al.  A 10-Gb/s CMOS clock and data recovery circuit with a half-rate linear phase detector , 2001, IEEE J. Solid State Circuits.

[8]  Hoi-Jun Yoo,et al.  A 4-Gb/s CMOS clock and data recovery circuit using 1/8-rate clock technique , 2003 .

[9]  B. Razavi,et al.  Analysis and modeling of bang-bang clock and data recovery circuits , 2004, IEEE Journal of Solid-State Circuits.

[10]  H.S. Muthali,et al.  A CMOS 10-gb/s SONET transceiver , 2004, IEEE Journal of Solid-State Circuits.

[11]  J. Fisher,et al.  A 10 Gb/s SONET-compliant CMOS transceiver with low cross-talk and intrinsic jitter , 2004, 2004 IEEE International Solid-State Circuits Conference (IEEE Cat. No.04CH37519).