Fault coverage estimation model for partially testable multichip modules

This paper proposes a simple and efficient model for designers to estimate fault coverage for partially testable MCMs. This model relates fault coverage, test methodology, and the ratio and distribution of DFT dies (dies with design for testability features) in an MCM. Experimental results show that our model can efficiently predict the fault coverage of a partially testable MCM with less than 5% deviation. In addition, the upper bound for fault coverage is also analyzed to guide the designers to know when to stop the effort in planning the use of DFT dies. Two defect level estimation models which relate fault coverage and manufacturing yield for measuring the test quality of MCMs under equiprobable and non-equiprobable faults, respectively, are also presented and evaluated.

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