Concurrent Error Detection and Fault Location in an

This paper presents a new approach for concur- rent error detection in a homogeneous architecture for the computation of the complex N-point fast Fourier transform (FFT) in radix-2. The proposed approach is based on the re- lationship between cell computations. It is proved that 100% probability of detection is possible. Overhead issues for hard- ware and timing are addressed. It is proved that hardware overhead for concurrent error detection is 50% compared to a fault-intolerant complex two-point implementation. A modest time overhead is encountered for error detection and fault lo- cation. Error detection can be accommodated on-line and on a component basis (multiplier or adderhbtractor); full fault lo- cation is accomplished by a roving technique. The proposed technique can be efficiently accommodated in a homogeneous layout. A two-phase reconfiguration policy for the proposed ar- chitecture is presented. It is proved that switching and routing overhead is modest, while achieving a significant reliability improvement over previous approaches.

[1]  Jacob A. Abraham,et al.  Fault-Tolerant FFT Networks , 1988, IEEE Trans. Computers.

[2]  Miroslaw Malek,et al.  A Fault-Tolerant FFT Processor , 1988, IEEE Trans. Computers.

[3]  Janak H. Patel,et al.  Concurrent Error Detection in ALU's by Recomputing with Shifted Operands , 1982, IEEE Transactions on Computers.

[4]  Fabrizio Lombardi,et al.  On an improved design approach for C-testable orthogonal iterative arrays , 1988, IEEE Trans. Comput. Aided Des. Integr. Circuits Syst..

[5]  David A. Huffman,et al.  Testing for Faults in Cellular Logic Arrays , 1972 .

[6]  Earl E. Swartzlander,et al.  Defect tolerance and yield for a wafer scale FFT processor system , 1991, 1991 Proceedings, International Conference on Wafer Scale Integration.

[7]  G. Goto,et al.  A wafer-scale 170000-gate FFT processor with built-in test circuits , 1988 .

[8]  Carlos R. P. Hartmann,et al.  A novel concurrent error detection scheme for FFT networks , 1990, [1990] Digest of Papers. Fault-Tolerant Computing: 20th International Symposium.

[9]  Yves Crouzet,et al.  Physical Versus Logical Fault Models MOS LSI Circuits: Impact on Their Testability , 1980, IEEE Transactions on Computers.

[10]  Miroslaw Malek,et al.  Real-Time Diagnosis of Homogeneous Systems , 1985, RTSS.

[11]  Sudhakar M. Reddy,et al.  A Testable Design of Iterative Logic Arrays , 1981, IEEE Transactions on Computers.

[12]  Chris Jesshope.  Wafer Scale Integration , 1986 .

[13]  H. T. Kung.  Why systolic architectures? , 1982, Computer.

[14]  Michel Minoux,et al.  Graphs and Algorithms , 1984 .

[15]  Janak H. Patel,et al.  A Minimum Test Set for Multiple Fault Detection in Ripple Carry Adders , 1987, IEEE Transactions on Computers.

[16]  Jacob A. Abraham,et al.  Algorithm-Based Fault Tolerance for Matrix Operations , 1984, IEEE Transactions on Computers.

[17]  Larry L. Kinney,et al.  C-Testability of Two-Dimensional Iterative Arrays , 1986, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems.

[18]  Kai Hwang,et al.  Computer arithmetic: Principles, architecture, and design , 1979 .