Identifying the Source of BW Failures in High-Frequency Linear Analog Circuits Based on S-Parameter Measurements

High-frequency linear analog circuits are widely used in high-speed and wireless radio frequency communication circuits as front-end devices. The small-signal model of transistors is typically used to evaluate the bandwidth (BW) of such devices during design iterations. However, since such devices typically push the boundaries of the manufacturing processes, small-signal parameters are not entirely reliable, leading to systematic silicon failures due to inadequate BW. With increasing uncertainties in the modeling and processing of semiconductor devices, it is essential that the sources of BW failures be identified immediately once the devices are manufactured. This paper presents a methodology to diagnose the systematic BW failures in linear broadband analog circuits. The most important small-signal parameters of internal transistors are determined to enable the redesign process. An evolutionary algorithm specifically designed to mimic the expected errors is used to ensure fast convergence to the correct solution. Sensitivity analysis is used to determine the set of the most impactful small-signal parameters and to guide the evolutionary search. A weighed average approach is also used to improve the accuracy for large-scale systems. Experimental results indicate that the proposed algorithm determines the parameters accurately and scales well in terms of accuracy and computation time

[1]  Hiroaki Kurokawa,et al.  Digital logic synthesis using genetic algorithms , 1997 .

[2]  C. L. Chen,et al.  Linear Dependencies in Linear Feedback Shift Registers , 1986, IEEE Transactions on Computers.

[3]  Noushin Riahi,et al.  A high speed trans-impedance amplifier using 0.13 /spl mu/m triple-well CMOS technology , 2004, 2004 IEEE International Symposium on Circuits and Systems (IEEE Cat. No.04CH37512).

[4]  Tom W. Chen,et al.  Optimization of individual well adaptive body biasing (IWABB) using a multiple objective evolutionary algorithm , 2005, Sixth international symposium on quality electronic design (isqed'05).

[5]  Michael D. Vose,et al.  The simple genetic algorithm - foundations and theory , 1999, Complex adaptive systems.

[6]  Seonghearn Lee,et al.  A semianalytical parameter extraction of a SPICE BSIM3v3 for RF MOSFET's using S-parameters , 2000 .

[7]  Rob A. Rutenbar,et al.  Anaconda: simulation-based synthesis of analog circuits viastochastic pattern search , 2000, IEEE Trans. Comput. Aided Des. Integr. Circuits Syst..

[8]  Leon O. Chua,et al.  Computer-Aided Analysis Of Electronic Circuits , 1975 .

[9]  P. L. Werner,et al.  Extraction of SPICE-type equivalent circuits of microwave components and discontinuities using the genetic algorithm optimization technique , 2000 .

[10]  F. Ellinger,et al.  A low-power 20-GHz 52-dB/spl Omega/ transimpedance amplifier in 80-nm CMOS , 2004, IEEE Journal of Solid-State Circuits.

[11]  Helmut Graeb,et al.  A fast method for identifying matching-relevant transistor pairs , 2001, Proceedings of the IEEE 2001 Custom Integrated Circuits Conference (Cat. No.01CH37169).

[12]  BEREND W MEIJER,et al.  Testability analysis of analog systems - Computer-Aided Design of Integrated Circuits and Systems, IEEE Transactions on , 2004 .

[13]  R. Lefferts,et al.  An integrated test chip for the complete characterization and monitoring of a 0.25/spl mu/m CMOS technology that fits into five scribe line structures 150/spl mu/m by 5000/spl mu/m , 2003, International Conference on Microelectronic Test Structures, 2003..

[14]  R. Weigel,et al.  On the synthesis of equivalent circuit models for multiports characterized by frequency-dependent parameters , 2002, 2002 IEEE MTT-S International Microwave Symposium Digest (Cat. No.02CH37278).

[15]  Daniel D. Gajski,et al.  High ― Level Synthesis: Introduction to Chip and System Design , 1992 .

[16]  Hans G. Kerkhoff,et al.  TASTE: a tool for analog system testability evaluation , 1988, International Test Conference 1988 Proceeding@m_New Frontiers in Testing.

[17]  Y. Rolain,et al.  Identifying S-parameter models in the Laplace domain for high frequency multiport linear networks , 1998, 1998 IEEE MTT-S International Microwave Symposium Digest (Cat. No.98CH36192).

[18]  Tapan K. Sarkar,et al.  A discussion of various approaches to the identification/approximation problem , 1982 .

[19]  Andrzej J. Strojwas,et al.  In-line yield prediction methodologies using patterned wafer inspection information , 1998 .

[20]  P. Bendix,et al.  Extraction of high-frequency equivalent circuit parameters of submicron gate-length MOSFET's , 1998 .

[21]  Y. L. Chow,et al.  Genetic algorithms applied to microwave circuit optimization , 1997, Proceedings of 1997 Asia-Pacific Microwave Conference.

[22]  Bozena Kaminska,et al.  Analog circuit fault diagnosis based on sensitivity computation and functional testing , 1992, IEEE Design & Test of Computers.

[23]  In-Dal Song,et al.  Multi-Gbit/s CMOS Transimpedance Amplifier with Integrated Photodetector for Optical Interconnects , 2004 .

[24]  Safieddin Safavi-Naeini,et al.  A hybrid evolutionary programming method for circuit optimization , 2005, IEEE Transactions on Circuits and Systems I: Regular Papers.

[25]  Willy M. C. Sansen,et al.  Modeling of the MOS transistor for high frequency analog design , 1989, IEEE Trans. Comput. Aided Des. Integr. Circuits Syst..

[26]  Minh N. Do,et al.  Youn-Long Steve Lin , 1992 .

[27]  S.P. Voinigescu,et al.  Direct extraction methodology for geometry-scalable RF-CMOS models , 2004, Proceedings of the 2004 International Conference on Microelectronic Test Structures (IEEE Cat. No.04CH37516).

[28]  F. Brauchler,et al.  Scalable RF Si MOSFET distributed lumped element model based on BSIM3v3 , 1997 .

[29]  Andrzej J. Strojwas,et al.  Monitoring multistage integrated circuit fabrication processes , 1996 .

[30]  Qiwen Yang,et al.  Parameter estimation for time-varying system based on improved genetic algorithm , 2002, IEEE 2002 28th Annual Conference of the Industrial Electronics Society. IECON 02.