AIDA: Layout-aware analog circuit-level sizing with in-loop layout generation

Abstract This paper presents AIDA, an analog integrated circuit design automation environment, which implements a design flow from a circuit-level specification to physical layout description. AIDA results from the integration of two in-house tools, namely, AIDA-C and AIDA-L. AIDA-C consists of an innovative layout-aware optimization-based methodology for automatic sizing of analog ICs. AIDA-L, the layout generator, implements a fully automated layout generation methodology. AIDA-L provides two alternative floorplanners, a template-based and an optimization-based. The placed modules, whose layouts are spawned by the in-house module generator, are fed together with the node electric-currents to the electromigration-aware multi-port Router that finalizes the layout. Finally, the integration of AIDA environment on the traditional analog IC design flow is discussed, and demonstrated for analog IC sizing and layout generation. Results are validated by industrial simulators and analysis tools, such as, HSPICE®, SPECTRE®, ELDO® or CALIBRE®.

[1]  Nuno Horta,et al.  LAYGEN II—Automatic Layout Generation of Analog Integrated Circuits , 2013, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems.

[2]  Nuno Horta,et al.  Electromigration-aware analog Router with multilayer multiport terminal structures , 2014, Integr..

[3]  Ranga Vemuri,et al.  Fast, layout-inclusive analog circuit synthesis using pre-compiled parasitic-aware symbolic performance models , 2004, Proceedings Design, Automation and Test in Europe Conference and Exhibition.

[4]  Georges Gielen,et al.  CAD tools for embedded analogue circuits in mixed-signal integrated systems on chip , 2005 .

[5]  Francisco V. Fernández,et al.  A two-step layout-in-the-loop design automation tool , 2015, 2015 IEEE 13th International New Circuits and Systems Conference (NEWCAS).

[6]  Nuno Horta,et al.  Design automation tasks scheduling for enhanced parallel execution of a state-of-the-art layout-aware sizing approach , 2016, 2016 Design, Automation & Test in Europe Conference & Exhibition (DATE).

[7]  Francisco V. Fernández,et al.  Area optimization on fixed analog floorplans using convex area functions , 2013, 2013 Design, Automation & Test in Europe Conference & Exhibition (DATE).

[8]  Helmut E. Graeb,et al.  Constraint-Based Layout-Driven Sizing of Analog Circuits , 2011, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems.

[9]  Helmut Graeb,et al.  Analog Layout Synthesis: A Survey of Topological Approaches , 2010 .

[10]  Ramy Iskander,et al.  A Python-based layout-aware analog design methodology for nanometric technologies , 2011, 2011 IEEE 6th International Design and Test Workshop (IDT).

[11]  João Goes,et al.  Single-stage amplifiers with gain enhancement and improved energy-efficiency employing voltage-combiners , 2013, 2013 IFIP/IEEE 21st International Conference on Very Large Scale Integration (VLSI-SoC).

[12]  Ricardo Povoa,et al.  Floorplan-aware analog IC sizing and optimization based on topological constraints , 2015, Integr..

[13]  Kaushik Roy,et al.  An Analytical Fringe Capacitance Model for Interconnects Using Conformal Mapping , 2006, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems.

[14]  E. Roca,et al.  An automated layout-aware design flow , 2012, 2012 International Conference on Synthesis, Modeling, Analysis and Simulation Methods and Applications to Circuit Design (SMACD).

[15]  Kun Lu,et al.  Comprehensive Generation of Hierarchical Placement Rules for Analog Integrated Circuits , 2011, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems.

[16]  N. Horta,et al.  AIDA: Automated analog IC design flow from circuit level to layout , 2012, 2012 International Conference on Synthesis, Modeling, Analysis and Simulation Methods and Applications to Circuit Design (SMACD).

[17]  Ranga Vemuri,et al.  Efficient Synthesis of a Uniformly Spread Layout Aware Pareto Surface for Analog Circuits , 2009, 2009 22nd International Conference on VLSI Design.

[18]  Nuno Horta,et al.  Extraction and application of wiring symmetry rules to route analog multiport terminals , 2015, 2015 IEEE International Symposium on Circuits and Systems (ISCAS).

[19]  Michiel Steyaert,et al.  A layout-aware synthesis methodology for RF circuits , 2001, IEEE/ACM International Conference on Computer Aided Design. ICCAD 2001. IEEE/ACM Digest of Technical Papers (Cat. No.01CH37281).

[20]  Nuno Horta,et al.  Multi-objective optimization of analog integrated circuit placement hierarchy in absolute coordinates , 2015, Expert Syst. Appl..

[21]  Francisco V. Fernández,et al.  An Integrated Layout-Synthesis Approach for Analog ICs , 2008, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems.

[22]  Nuno Horta,et al.  Layout-aware sizing of analog ICs using floorplan & routing estimates for parasitic extraction , 2015, 2015 Design, Automation & Test in Europe Conference & Exhibition (DATE).