Reconciling the IC test and security dichotomy
暂无分享,去创建一个
Jeyavijayan Rajendran | Ramesh Karri | Ozgur Sinanoglu | Yiorgos Makris | Yier Jin | Naghmeh Karimi | K. Huang | O. Sinanoglu | R. Karri | K. Huang | Y. Makris | Yier Jin | Naghmeh Karimi | Jeyavijayan Rajendran
[1] Mark Mohammad Tehranipoor,et al. Sensitivity analysis to hardware Trojans using power supply transient signals , 2008, 2008 IEEE International Workshop on Hardware-Oriented Security and Trust.
[2] Heng Tao Shen,et al. Principal Component Analysis , 2009, Encyclopedia of Biometrics.
[3] Kaushik Roy,et al. Multiple-parameter side-channel analysis: A non-invasive hardware Trojan detection approach , 2010, 2010 IEEE International Symposium on Hardware-Oriented Security and Trust (HOST).
[4] Scott A. Mahlke,et al. Data Access Partitioning for Fine-grain Parallelism on Multicore Architectures , 2007, 40th Annual IEEE/ACM International Symposium on Microarchitecture (MICRO 2007).
[5] Yu Cao,et al. Modeling and minimization of PMOS NBTI effect for robust nanometer design , 2006, 2006 43rd ACM/IEEE Design Automation Conference.
[6] Jarrod A. Roy,et al. EPIC: Ending Piracy of Integrated Circuits , 2008, 2008 Design, Automation and Test in Europe.
[7] Yiorgos Makris,et al. Hardware Trojans in Wireless Cryptographic ICs , 2010, IEEE Design & Test of Computers.
[8] Swarup Bhunia,et al. HARPOON: An Obfuscation-Based SoC Design Methodology for Hardware Protection , 2009, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems.
[9] D. Das,et al. Semiconductor Manufacturers' Efforts to Improve Trust in the Electronic Part Supply Chain , 2007, IEEE Transactions on Components and Packaging Technologies.
[10] Berk Sunar,et al. Trojan Detection using IC Fingerprinting , 2007, 2007 IEEE Symposium on Security and Privacy (SP '07).
[11] Yu Cao,et al. Predictive Modeling of the NBTI Effect for Reliable Design , 2006, IEEE Custom Integrated Circuits Conference 2006.
[12] Yiorgos Makris,et al. Hardware Trojan detection using path delay fingerprint , 2008, 2008 IEEE International Workshop on Hardware-Oriented Security and Trust.
[13] Mark Mohammad Tehranipoor,et al. Power supply signal calibration techniques for improving detection resolution to hardware Trojans , 2008, 2008 IEEE/ACM International Conference on Computer-Aided Design.
[14] Yiorgos Makris,et al. Error Moderation in Low-Cost Machine-Learning-Based Analog/RF Testing , 2008, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems.
[15] Sudhakar M. Reddy,et al. On Delay Fault Testing in Logic Circuits , 1987, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems.
[16] Robert P. Dick,et al. Minimization of NBTI performance degradation using internal node control , 2009, 2009 Design, Automation & Test in Europe Conference & Exhibition.
[17] Jaume Abella,et al. Penelope: The NBTI-Aware Processor , 2007, 40th Annual IEEE/ACM International Symposium on Microarchitecture (MICRO 2007).
[18] M. Pecht,et al. Bogus: electronic manufacturing and consumers confront a rising tide of counterfeit electronics , 2006, IEEE Spectrum.
[19] Soumitra Bose,et al. Delay Test Quality Evaluation Using Bounded Gate Delays , 2007, 25th IEEE VLSI Test Symposium (VTS'07).
[20] Taewhan Kim,et al. A fine-grained technique of NBTI-aware voltage scaling and body biasing for standard cell based designs , 2011, 16th Asia and South Pacific Design Automation Conference (ASP-DAC 2011).
[21] Yu Cao,et al. An efficient method to identify critical gates under circuit aging , 2007, 2007 IEEE/ACM International Conference on Computer-Aided Design.
[22] N. Moshtagh. MINIMUM VOLUME ENCLOSING ELLIPSOIDS , 2005 .
[23] Swarup Bhunia,et al. Self-referencing: A Scalable Side-Channel Approach for Hardware Trojan Detection , 2010, CHES.
[24] Yiorgos Makris,et al. Parametric counterfeit IC detection via Support Vector Machines , 2012, 2012 IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems (DFT).
[25] I. Jolliffe. Principal Component Analysis , 2002 .
[26] James F. Plusquellic,et al. REBEL and TDC: Two embedded test structures for on-chip measurements of within-die path delay variations , 2011, 2011 IEEE/ACM International Conference on Computer-Aided Design (ICCAD).
[27] Jeyavijayan Rajendran,et al. Logic encryption: A fault analysis perspective , 2012, 2012 Design, Automation & Test in Europe Conference & Exhibition (DATE).
[28] Jeyavijayan Rajendran,et al. Security analysis of logic obfuscation , 2012, DAC Design Automation Conference 2012.