Enhanced Parallel Hybrid Converter With DC Ripple Minimization Control

The parallel hybrid converter (PHC) offers compact and highly efficient converter solution for high-power applications. One of the major drawbacks of PHC is the requirement of a bulky dc-side inductor to minimize the dc ripples. Modified third-harmonic injection method and zero-sequence voltage injection method can minimize these ripples. However, their complete mitigation is not possible with these existing methods. In this letter, a new control scheme is proposed, which eliminates the dc-side voltage/current ripple by injecting a suitable common-mode voltage into the chain-link of PHC. The presented method also increases the ac output voltage for a given dc-link voltage and effective utilization of the available dc voltage is achieved. Hence, an enhanced-PHC (EPHC) topology is achieved. The analyses presented are verified using PSCAD/EMTDC. A 25-level EPHC–HVdc system is also developed to substantiate the applicability of the proposed method for HVdc system. Experimental studies are performed using a three-phase 13-level laboratory prototype in order to verify the simulation outcomes and the findings acquired are observed to be in agreement with the simulation studies.