A chip-level electrothermal simulator for temperature profile estimation of CMOS VLSI chips
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In this paper, we present a chip-level electrothermal simulator, ILLIADS-T. It aims at finding the steady-state CMOS VLSI chip temperature profile and the corresponding circuit performance. With this tool, temperature-related reliability problems of VLSI chips can be accurately predicted to guide the module placement, packaging, as well as the timing verification.
[1] Y. C. Lee,et al. Internal thermal resistance of a multi-chip packaging design for VLSI-based systems , 1988 .
[2] A. L. Palisoc,et al. Thermal analysis of integrated circuit devices and packages , 1989 .
[3] Sung-Mo Kang,et al. Circuit-level electrothermal simulation of electrical overstress failures in advanced MOS I/O protection devices , 1994, IEEE Trans. Comput. Aided Des. Integr. Circuits Syst..
[4] Sung-Mo Kang,et al. Circuit-Level Electrothermal Simulation , 1995 .